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"; PHY; physical layer; radio; wireless local area network; WLAN
#
# ISBN-10 / ASIN:
# Number Of Pages:
# Publication Date:
# Publisher: Auerbach Publications
(2018) 1049pp. 978-0-12-812275-4
-
-3A
-3E
-4
0387961313
0444825371
0470319895
0521853508
10 Gigabit Ethernet
100 Gigabit Ethernet
13.1
1402073879
153
1989
1991.
1996; Pub: Prentice Hall
1999 Edition
2.5 Gigabit Ethernet
200 Gigabit Ethernet
2003-01
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers;2004; ; ;10.1109/RFIC.2004.1320548
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512);2004;1; ;10.1109/ISCAS.2004.1328296
2004.11.
2005.1
2006年
2007.03.
2007年
2008
2008.
2008年
2009 IEEE Custom Integrated Circuits Conference;2009; ; ;10.1109/CICC.2009.5280848
2009 Symposium on VLSI Circuits;2009; ; ;
2009.10.
2009.6
2009.9
2009年
2010 IEEE International Solid-State Circuits Conference - (ISSCC);2010; ; ;10.1109/ISSCC.2010.5433970
2010.06
2010.06.
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS);2012; ; ;10.1109/MWSCAS.2012.6291943
2012.11.
2013.06.
2013.11.
2014.01.
2014.04.
2014.07.
2016 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB);2016; ; ;10.1109/ICUWB.2016.7790413
2016.07.
249
25 Gigabit Ethernet
256-QAM
270
2e
377页
3A DSP
3e
40 Gigabit Ethernet
400 Gigabit Ethernet
448页
476
489页
497页
5 Gigabit Ethernet
502页
563页
582页
668页
7 series
7-series
732页
7series
843
978-1-60807-557-7
978-1-60807-896-7
978-1-63081-910-1
9780070552210
9780136024583
9780136024989
9780444825377
9780470319895
9780521873024
9780819483263
9780849372421
9781118841099 COMPUTER PRINCIPLES AND DESIGN IN VERILOG HDL
981429165X
<formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> oscillator
<formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> tank
<italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">gₘ</italic>-boosting
[dita]
[General Information]
_hw.tcl
A 7
A detailed tutorial on Sigma-Delta analog-to-digital converters and modulators. Learn more about over-sampling
A new configuration for realization of a stabilized bandgap voltage is described. The new two-transistor circuit uses collector current sensing to eliminate errors due to base current. Because the stabilized voltage appears at a high impedance point
A temperature-compensated voltage reference that provides numerous advantages over zener diodes is described along with the implementation of thermal overload protection for monolithic circuits. The application of these and other advanced design techniques to IC voltage regulators is covered
A-7
a/d converters
A7
Accuracy
acpr
adaptive
Adaptive <sc xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">on</sc>-time (AOT) control
Adaptive biasing
ads
ADSP-TS101
ADSP-TS201
advanced control
Advanced Microcontroller Bus Architecture AMBA APB AXI eXtensible Interface
ADVANCED PROGRAMMING IN THE UNIX ENVIRONMENT
AHB
AHB Interconnect
AHB Peripherals
AHB-Lite Advanced High-performance Bus (AHB) Interconnect for Cortex-M Processors and Peripherals via Advanced Peripheral Bus (APB) Bridge Interface
Altera
AMBA
AMBA Advanced Peripheral Bus Protocol
ampifiers
amplifiers
AN
analog and mixed-signal full-chip verification
analog and RF block-level development with flexible and reliable abstraction
Analog Circuit Design Volume 2
Analog Circuit Design Volume Three
analog devices
Analog-to-digital converter;energy efficient;low power;successive approximation register
and AMBA 4 AXI User Guide
and an example of a practical design is given.
and biasing for optimum temperature performance. The performance of the monolithic circuit
and controlling off-chip devices. Components available in Platform Designer incorporate these standard interfaces.
and CP1 with RF simulator
and decimation filters.
and detection applications.
and fabrication considerations for high-density integrated circuits in nanometer CMOS processes
and it analyzes circuit architectures that are suitable for analog building blocks. Highlighting various design challenges
and Makers
and Nichols
and optimizing Nios II processor-based embedded systems using Intel provided tools.
and parameters of the Triple-Speed Ethernet Intel FPGA IPcore. The Triple-Speed Ethernet Intel FPGA IP core is a configurable intellectual property (IP) core that incorporates a 10/100/1000-Mbps Ethernet media access controller (MAC) and an optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded PMA built with either on-chip transceiver I/Os or LVDS I/Os.
and recommends design styles and practices for developing
and state space variable method. Presentations are limited to linear
and the instruction set.
and using the waveform viewer to analyze and debug a design. Documents behavioral simulation of an RTL design as well as functional and timing simulation of synthesized and implemented designs.
and Virtex-7 FPGAs. Can be configured as tx or rx. Supports sharing GTX/ GTH transceiver between a transmitter and receiver.
APB
application and analysis of computational ideas and methods.
Application Notes
Application Reports
Applications
architectural exploration
area-efficient high-performance FIR filters utilizing either Multiply-Accumulate (MAC) or Distributed Arithmetic (DA) architectures.
ARM
ARM AMBA 5 AHB Protocol Specification AHB5
Arria 10
Artech House
Artix
Artix 7
Artix-7
Artix7
as amended by IEEE Stds
as measured at the MAC data SAP.
as part of the Vivado Design Suite
ASB
assertions
Asynchronous integral control
ATLANTIS PRESS
attachment unit interface
AUI
Auto-Negotiation
automation control
Avalon Cores
Avalon Memory-Mapped
Avalon Streaming
Avalon Tri-state Conduit Component
Avalon-TC
AXI
AXI BAR
AXI Interconnect
AXI Peripherals
AXI3
AXI4
AXI4-Lite
AXI4-Stream
Backplane Ethernet
Bandwidth
Bandwidth enhancement
beamforming
behavioral
benemale
BFM
bidirectional pins
bingdian001.com
Bode–Fano
Booting Methods
bridge
broadband
broadband amplifier
brush–commutator DC machines
buck converter
Buffer circuits
Bus functional model
C1WCD6VZebYu*DsiffI97^LlEcL*MyZbDj$JnPs$GdjZDFRZ9JY8hbZeugZ0
Cache and Memory Interface
Cambridge University Press
Casex Statements
Catalog
Changes and additions to IEEE Std 802.11
Charge pump (CP);delta&#8211;sigma;dynamic mismatch;dynamic mismatch corner frequency;flicker noise;flicker noise corner frequency;fractional-N frequency synthesizer (Frac-N);frequency synthesizer;gain mismatch;gain mismatch corner frequency;phase frequency detector (PFD);phase noise;reset delay mismatch;rms phase error;spurs;thermal noise;voltage-controlled oscillator (VCO)
Charge pump (CP);fractional-<formula formulatype="inline"><tex Notation="TeX">$N$</tex> </formula> phase-locked loops (PLLs);phase noise
chopper-stabilized amplifiers
Choppers;CMOS analog integrated circuits;operational amplifiers
Chopping
Circuit
Circuit modeling
circuit simulation platform
Circuit Simulations
Circuits
CIRCUITS AND DEVICES
clock
CMOS
CMOS bandgap reference
CMOS integrated circuits
CMOS; CGWO; optimization technique; operational amplifier; aspect ratio; power dissipation
COM051360 - COMPUTERS / Programming Languages / Python
COM070000 - COMPUTERS / User Interfaces
COM087020 - COMPUTERS / Desktop Applications / Design and Graphics
Combinational Circuits
combiner
Compact Models for Circuit Simulation
compiler
Component Editor
components
Compositor: Windfall Software
compression point
Computational electromagnetic
Computer Organization and Design: The Hardware/Software Interface
Computer-aided circuit analysis
Computing
Conditional Operator
conduit
Control loops
CORDIC
CORE Generator
core-clocking
Coregen
cores
correlated double sampling
corruption semantics
Cortex-M
CP1
crystal oscillators
current amplifier
Current mirror
curvature correction
Cyclone 10
cyclostationary noise
D/A Converters
data processing
Data Sheet
dc–dc buck converter
debug
debugging
December 2022
Describes the GTX/GTH transceivers in the 7 series devices.
Describes using the Vivado® simulator as both a stand-alone tool
design
design and verification
design cycle
design guidelines are suggested and test results are presented.
design intent
design methods
DesignWare Foundation Cores
DesignWare Synthesizable Components for AMBA 3 AXI
Device Technology
Devices & Systems
Digital beamforming (DBF)
Digital Logic
Digital Systems
direct digital synthesizer
discontinuous conduction mode (DCM)
distortion
Distributed Arithmetic
doc.type.documentation.ref
double clock time (DCT) control
ds249
DS534
DS558
ds768
ds814
DS843
DSM
DTE Power via the MDI
dual or quad SPI protocol.
dual-band
duplex
Dword
dynamic biasing
E-band
EDA应用技术
EDS
EE-Notes
EE247 Lecture Notes
eesof
electric machine circuit models
electric machines electromagnetics
Electromagnetics
Electronics Explained: Fundamentals for Engineers
electrostatic discharge protection
Embedded System
End Point
endian
Endpoint
Energy Efficient Ethernet
EPoC
EPON
EPON Protocol over Coax
Equality Operators
eSPI Core
Ethernet
Ethernet in the First Mile
Ethernet passive optical network
EURASIP Journal on Wireless Communications and Networking
evm
executable
express traffic
families
Fast Ethernet
fifth-generation (5G) communication
Figure-of-merit
filtering
FinFET
FinFET Device Operation
FinFET Device Technology
finite element analysis
FIR
First Edition (2013)
First Edition (2014) 1109pp 978-0-12-800001-4
flux orientation control
FM
FoM
FoMA
FPGA
Fractional spur
Frequency response
frequency response methods of analysis including Bode
frequency synthesis
functional
functional specification
gain and frequency response parameters
Gen 1/2/3 configurations.
Gen1
Gen2
Gen3
generic tri-state controller
Gigabit Ethernet
gm/ID methodology
graphical
gth
gtx
gty
HanWang PDF Technology
Hard IP for PCI Express Endpoint and Root Port
hi-Z
high efficiency
high throughput
high throughput; MAC; medium access control; MIMO; MIMO-OFDM; "multiple input
high-Z
hybrid biasing
Hybrid system
IEEE 1801™
IEEE 802.11ac™
IEEE 802.3
IEEE 802.3™
IEEE Circuits and Systems Magazine;2014;14;2;10.1109/MCAS.2014.2314263
IEEE Custom Integrated Circuits Conference 2006;2006; ; ;10.1109/CICC.2006.320979
IEEE International Sympoisum on Circuits and Systems;1991; ; ;10.1109/ISCAS.1991.176049
IEEE Journal of Solid-State Circuits;1990;25;6;10.1109/4.62165
IEEE Journal of Solid-State Circuits;1993;28;12;10.1109/4.262000
IEEE Journal of Solid-State Circuits;2000;35;3;10.1109/4.826814
IEEE Journal of Solid-State Circuits;2001;36;3;10.1109/4.910480
IEEE Journal of Solid-State Circuits;2002;37;11;10.1109/JSSC.2002.803936
IEEE Journal of Solid-State Circuits;2002;37;8;10.1109/JSSC.2002.800925
IEEE Journal of Solid-State Circuits;2006;41;12;10.1109/JSSC.2006.884195
IEEE Journal of Solid-State Circuits;2010;45;4;10.1109/JSSC.2010.2042254
IEEE Microwave Magazine;2010;11;1;10.1109/MMM.2009.935203
IEEE Microwave Magazine;2019;20;5;10.1109/MMM.2019.2898022
IEEE Solid-State Circuits Magazine;2016;8;2;10.1109/MSSC.2016.2543061
IEEE Solid-State Circuits Magazine;2018;10;2;10.1109/MSSC.2018.2822859
IEEE Transactions on Circuits and Systems I: Regular Papers;2005;52;2;10.1109/TCSI.2004.841594
IEEE Transactions on Circuits and Systems I: Regular Papers;2010;57;8;10.1109/TCSI.2009.2039832
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing;2001;48;4;10.1109/82.933799
implementation
in
Inc.
increased productivity and throughput
induction machines transients
inductor
Inequality Operators
information exchange
Input resistance
Input Return Loss
Institution of Engineering
Integrated circuits
intercept point
intercept points
Interconnect
interface specification
Internal
Internally compensated CMOS op amps have been widely used in sampled-analog signal processing applications over the past several years. However
Internet of things (IoT)
interoperability
interpolation
IP
IP core
IP integrator
IP reuse
IP Version: 19.3.0. Describes the features
IP2
IP3
is reported.
ISBN 978-7-03-022031-8
ISBN-10:
ISBN-13:
ISBN-13: 978-7-5605-1884-2
ISBN-13: 9780387961316
ISBN-13: 9780470167588
ISBN-13: 9789814291651
ISBN: 0135309247; Date: May 22
ISBN: 7115150559
ISBN：9787121096075
ISBN：9787302211464
isolation
JEDEC
jitter
jitter extraction
JTAG Debug Module
K 7
K-7
K7
Keywords
Keywords- Advanced Design Systems
Kintex
Kintex 7
Kintex-7
Kintex7
L1 -gain performance
LAN
Laplace transforms and transfer functions
Leakage Currents
least squares and Monte Carlo methods. This book balances the development
level shifting
Linear and switching power
Linear integrated circuits
Linear Matrix Inequalities
linker
LMI technique
load-pull
local area network
LogiCORE
loss
low <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">IQ</italic> low dropout (LDO)
Low Noise Amplifier
Low voltage circuits
low-noise amplifier (LNA)
MAC
management
masking
massive multiple-input multiple-output (MIMO)
master bridge
MATERIALS
MATLAB
matlab 80
MATLAB exercises for robust and optimal control
MATLAB for Control System Engineers is designed as an introductory undergraduate or graduate course for science and engineering students of all disciplines. Control systems engineering is a multidisciplinary subject and presents a control engineering methodology based on mathematical fundamentals and stresses physical system modeling. The classical methods of control systems engineering are covered here using MATLAB software: matrix analysis
McGraw-Hill
MDI
media independent interface
medium dependent interface
memory bus design
Memory control
memory map
MEMS
Metal-Oxide-Semiconductor
Method
MIB
Micorsystems
micromechanical resonator
microprocessors
MII
millimeter-wave
millimeter-wave (mm-Wave)
MNL-AVABUSREF
mode selection
model reduction
Moderate inversion
Moments
monitor
Monolithic integrated circuits
MPMC
mSGDMA
multi-feed antenna
multi-point MAC control
multi-port
multi-user MIMO
multibeam system
multiple output
Multiple-Gate
multiplication factor
Multiply-Accumulate
Networks
networksynthesis
NimoDoc
Nios II
Nios II Debug
Nios II Processor Core
NMOS LDO
noise
noise cancellation
Noise Figure
noise shaping
Non-Blocking Assignments
noncontiguous frequency segments
none
numerical integration and differentiation
Nyquist
OCR-PDF
of
on-demand buffer
opamp
Opamp design
Operational amplifiers
optimal control
optimal electromagnetic design
oscillator
oscillator phase noise
Output resistance
Output Return Loss
Parasitic Elements
PCI Express
PCIe
PCS
PDF Attachment
PDF Creator
pdflib
PDFￗﾪﾻﾻￆ
Perl语言入门 第六版
PG153
phase and gain margin and bandwidth
phase dithering
phase generator
phase noise
phase to SIN/COS
phase-error correction
phase-locked loop (PLL)
PHY
physical coding sublayer
Physical Layer
physical medium attachment
physical medium dependent
piezoelectric resonator
pin-out flow
Platform Designer
PLL
PMA
PMD
PoDL
pole-zero analysis
Poles and zeros
power amplifier (PA)
power amplifiers (PAs).
power domains
Power engineering
power intent
power modes
Power over Data Lines
Power over Ethernet
power states
power-aware design
Predicting IP2
Principles of Sigma-Delta Modulation for Analog-to-Digital Converters
product.id.P10089
product.id.P10099
product.id.P10101
product.id.P10115
product.id.P10119
product.id.P10122
product.id.P11426
product.id.P11427
product.id.P11481
product.id.P11493
product.version.10.3c
product.version.v2020.1
Programming Model
progressive design refinement
Project Navigator
Proportional control
propulsion control
Publisher:
Publisher: O'Reilly Media
pulse-width-modulation (PWM) current mode control
Python
QSPI Controller Core
Qsys
quad
Quad SPI
Quartus Prime
radio frequency
Radio Frequency System Architecture and Design
reading and writing registers and memory
reconciliation sublayer
reference
Reference circuits
Reference interface specification PDF documentation for the AMBA AXI Protocol
Reference interface specification PDF documention for the AMBA4 AXI4-Stream Protocol
reference spur
Referex
Referex; Computer Science (General);Information Systems;Electrical and Electronic Engineering;
relaxation oscillator
repeater
retention
retention strategies
RF design
RF Simulation
rfic
Ring PLL
ring voltage-controlled oscillator (VCO)
robust and optimal control
robust control
robust control textbook
room temperature trim
root finding
root locus
root locus analysis and design
Root Port
rotational
RS
S 3
S 6
S-3
S-6
S3
S6
sample-reset loop filter
sampling noise
SBAA328
scaling
Scientific Computing; Taylor’s Theorem; Roundoff Errors; Error Propagation; Linear Systems; Root Finding; Interpolation; Numerical Integration; Numerical Differentiation; Initial Value Problems; Boundary Value Problems; Iterative Methods; Least Squares Problems; Monte Carlo Methods; Parallel Computing; MATLAB
Second Edition (2018) 408pp. 978-0-12-811641-8
second order systems approximations
Semiconductor
Semiconductor Physics
serdes
Serial Flash Controller Core
SiGe
sigma-delta adc topology
signal acquisition
signals
Simulation
simulator
slave bridge
Small Geometry FinFETs
SoC
some will apply specifically to our case in question.
Spartan
SpectreRF
speed control
SPI
SPI Core
Springer
Springer 2011
SSC
state-space techniques
Subject
surface PM synchronous machines
suspension control
sustaining amplifier
switched-capacitor
switched-capacitor tracking compensation
switched-loop filter (SLF)
SWRS040
SWRS040C
synchronous machine transients
system design
TEAM DDU
technical article
Technicians
TeX output 2014.03.17:1515
that features three low phase-noise VCOs with a fundamental frequency range of 3.0 GHz to 6.0 GHz and a programmable dual RF output divider stage which allows coverage from 46.875 MHz to 6 GHz.
The
the application to circuits with higher output voltage is simplified. Incorporation of the new two-transistor cell in a three-terminal 2.5-V monolithic reference is described. The complete circuit is outlined in functional detail together with analytical methods used in the design. The analytical results include sensitivity coefficients
The AXI Memory Mapped to PCI Express™ core is an interface between the AXI4 and PCI Express.
The AXI Quad SPI core connects the AXI4 interface to SPI slave devices which support the standard
The book presents design methods for analog integrated circuits with improved electrical performance. It describes different equivalent transistor models
The DDS (Direct Digital Synthesizer) Compiler core sources sinusoidal waveforms for use in many applications. A DDS consists of a Phase Generator and a SIN/COS Lookup Table.
The effects of pole-zero pairs (doublets) on the frequency response and settling time of operational amplifiers are explored using analytical techniques and computer simulation. It is shown that doublets which produce only minor changes in circuit frequency response can produce major changes in settling time. The importance of doublet spacing and frequency are examined. It is shown that settling time always improves as doublet spacing is reduced whereas the effect of doublet frequency is different for 0.1 and 0.01 percent error bands. Finally it is shown that simple analytical formulas can be used to estimate the influence of frequency doublets on amplifier settling time.
The numerous worked examples (over 400 problems and solutions) are intended to provide the reader with an awareness of the general applicability of control theory using MATLAB. An extensive bibliography to guide the students to further sources of information on control systems engineering using MATLAB is provided at the end of the book.
the other for buffer applications requiring wide common-mode input range. Small signal analysis is developed for the open-loop and PSRR responses of the two amplifiers. In addition
the popular two-stage op amp suffers from poor AC power supply rejection to one of the power rails. Two circuits are presented that overcome the power-supply rejection ratio (PSRR) problems of the earlier amplifier: one for virtual ground applications such as switched-capacitor integrators
the programming model
The specific processor that we analyze here is ADSP-TS201S from TigerSHARC® family of processors. Some of the subjects discussed here will apply to jitter in general
The STW81200 is a dual architecture frequency synthesizer (Fractional-N and Integer-N)
the text offers a complete understanding of architectural- and transistor-level design issues of analog integrated circuits. It examines important trends in the design of high-speed and power-efficient front-end analog circuits that can be used for signal conditioning
The Xilinx LogiCORE IP CORDIC core implements a generalized coordinate rotational digital computer (CORDIC) algorithm.
The Xilinx LogiCORE IP FIR Compiler core provides a common interface for users to generate highly parameterizable
Theory of Modeling and Simulation
Third Edition
Third Edition (2019) i-iii. doi:10.1016/B978-0-12-813370-5.00002-X
This amendment defines modifications to both the IEEE 802.11 PHY and MAC sublayer so that modes of operation can be enabled that are capable of much higher throughputs
This application note and accompanying source code shows designers how to create a very small PCIe to AXI bridge which supports 1 DWORD reads and writes from the host to the FPGA Endpoint
This core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.
This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices
This document describes how to most effectively use the Nios II Embedded Design Suite (EDS) tools
This IP core is used for building a PCI Express® Media Access Controller (MAC) layer. It supports 1/2/4/8/16-lane
This textbook covers essential numerical techniques including basic methods for linear systems
This user guide describes the embedded peripherals IP cores that work seamlessly with the Nios II processor.
TigerSHARC
Time series analysis
time-invariant continuous systems.
timing
topologies
topology
Training Kit
trans impedance amplifier
transceiver
transistor
translation
tri-state conduit
Triple-Speed Ethernet
tristate conduit
Tutorial
type field
UG-01073
ug476
ug774
ultra-low-quiescent current
ultralow-quiescent current
UltraScale
UltraScale architecture
ultrascale plus
UltraScale+
Updated for Intel Quartus Prime Design Suite: 18.1. Avalon interfaces simplify system design by allowing you to easily connect components in Intel FPGAs. The Avalon interface family defines interfaces appropriate for streaming high-speed data
Updated for Intel Quartus Prime Design Suite: 19.3
Updated for Intel Quartus Prime Design Suite: 19.4. This document provides information about the Nios II processor architecture
USB 2.0
USB 2.0 规范初探
User Guide
using a fraction of the resources of the fully featured AXI Memory Mapped to PCIe Gen2 bridge.
V 4
V 5
V 6
V 7
V-4
V-5
V-6
V-7
V4
V5
V6
V7
verification
Verification Academy - UVM Cookbook
verify
Verilog
Version N-2017.12-SP2
Version U-2022.12
very
VHDL
Virtex
Virtex 7
Virtex-7
Virtex7
Vivado
Vivado Design Suite
VLAN tag
voltage-controlled oscillator
voltage-domain models
We will explain how IP3 is generated and how its values are linked. Learn how IP3 and intermodulation are generated and why they are important.
Week inversion
which includes temperature coefficients of 5 ppm//spl deg/C over the military temperature range
wide load current range
wider bandwidth
Wiley
Wiley-IEEE Press
wireless
wireless communication
WISHBONE System-on-Chip (SoC)Interconnection Architecturefor Portable IP Cores
with a maximum throughput of at least 100 Mb/s
www.ebook3000.com
www.it-ebooks.info
XA
XDC
Xilinx大学合作计划指定教材
XSim
Y-factor
zc706
ZHCC347
ZHCP055
zyng
Zynq
Zynq-7000
【ISBN号】978-7-121-10991-1
【丛书名】国外电子与通信教材系列
【中图法分类号】TP3
【出版商】 北京市：电子工业出版社
【页 数】 319
一本开源指令集的指南
上架时间：2010-3-19
丛书名: 图解实用电子技术丛书
丛书名： 微电子与集成电路技术丛书
人民邮电出版社
作者： 魏廷存
关键字
冯新宇著.ADS射频电路设计与仿真入门及应用实例.北京：电子工业出版社
出版日期：2010 年3月
出版社: 人民邮电出版社
出版社: 科学出版社有限责任公司
出版社：清华大学出版社
动态系统-反馈控制
化工
北京航空航天大学出版社
同济大学数学系编.高等数学 第7版 上.北京：高等教育出版社
国外电子与通信教材系列
国外电子与通信教材系列; 电子工业出版社; 2009年; 383页
国家集成电路工程领域工程硕士系列教材
图形学
图灵电子与电气工程丛书
实用教程
射频电路-电路设计-计算机辅助设计-软件包
平装: 296页
平装: 620页
建筑
开本: 16开
开本：16开
微波技术 微波技术
控制之美 卷2
控制系统-高等学校-教材
数字信号处理
数字电子技术基础
数字电路－电路设计
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普通高等教育“十一五”国家级规划教材
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最优化算法-高等学校-教材
本书包括函数与极限、导数与微分等…….
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樊昌信，曹丽娜编著.通信原理 第7版.北京：国防工业出版社
模拟电路-电子技术-高等学校-教材
模拟集成电路-电路设计-高等学校-教材
清华大学信息科学技术学院教材——微电子光电子系列
清华大学出版社
清华搬双语教学用书
电子工业出版社
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科学出版社; 国家集成电路工程领域工程硕士系列教材; 2008年; 301页
科目
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阔永红.数字信号处理 时域离散随机信号处理.西安：西安电子科技大学出版社
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（美）亚历山大著.电路基础 第5版.北京：机械工业出版社
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（美）普利斯曼，（美）比利斯，（美）莫瑞著.开关电源设计.北京市：电子工业出版社
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（英）DouglasSelf著.音频功率放大器设计手册.北京市：人民邮电出版社
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ￂￖￌ￢
Exclude Tags
"; PHY; physical layer; radio; wireless local area network; WLAN
#
# ISBN-10 / ASIN:
# Number Of Pages:
# Publication Date:
# Publisher: Auerbach Publications
(2018) 1049pp. 978-0-12-812275-4
-
-3A
-3E
-4
0387961313
0444825371
0470319895
0521853508
10 Gigabit Ethernet
100 Gigabit Ethernet
13.1
1402073879
153
1989
1991.
1996; Pub: Prentice Hall
1999 Edition
2.5 Gigabit Ethernet
200 Gigabit Ethernet
2003-01
2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of Papers;2004; ; ;10.1109/RFIC.2004.1320548
2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512);2004;1; ;10.1109/ISCAS.2004.1328296
2004.11.
2005.1
2006年
2007.03.
2007年
2008
2008.
2008年
2009 IEEE Custom Integrated Circuits Conference;2009; ; ;10.1109/CICC.2009.5280848
2009 Symposium on VLSI Circuits;2009; ; ;
2009.10.
2009.6
2009.9
2009年
2010 IEEE International Solid-State Circuits Conference - (ISSCC);2010; ; ;10.1109/ISSCC.2010.5433970
2010.06
2010.06.
2012 IEEE 55th International Midwest Symposium on Circuits and Systems (MWSCAS);2012; ; ;10.1109/MWSCAS.2012.6291943
2012.11.
2013.06.
2013.11.
2014.01.
2014.04.
2014.07.
2016 IEEE International Conference on Ubiquitous Wireless Broadband (ICUWB);2016; ; ;10.1109/ICUWB.2016.7790413
2016.07.
249
25 Gigabit Ethernet
256-QAM
270
2e
377页
3A DSP
3e
40 Gigabit Ethernet
400 Gigabit Ethernet
448页
476
489页
497页
5 Gigabit Ethernet
502页
563页
582页
668页
7 series
7-series
732页
7series
843
978-1-60807-557-7
978-1-60807-896-7
978-1-63081-910-1
9780070552210
9780136024583
9780136024989
9780444825377
9780470319895
9780521873024
9780819483263
9780849372421
9781118841099 COMPUTER PRINCIPLES AND DESIGN IN VERILOG HDL
981429165X
<formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> oscillator
<formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> tank
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[dita]
[General Information]
_hw.tcl
A 7
A detailed tutorial on Sigma-Delta analog-to-digital converters and modulators. Learn more about over-sampling
A new configuration for realization of a stabilized bandgap voltage is described. The new two-transistor circuit uses collector current sensing to eliminate errors due to base current. Because the stabilized voltage appears at a high impedance point
A temperature-compensated voltage reference that provides numerous advantages over zener diodes is described along with the implementation of thermal overload protection for monolithic circuits. The application of these and other advanced design techniques to IC voltage regulators is covered
A-7
a/d converters
A7
Accuracy
acpr
adaptive
Adaptive <sc xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">on</sc>-time (AOT) control
Adaptive biasing
ads
ADSP-TS101
ADSP-TS201
advanced control
Advanced Microcontroller Bus Architecture AMBA APB AXI eXtensible Interface
ADVANCED PROGRAMMING IN THE UNIX ENVIRONMENT
AHB
AHB Interconnect
AHB Peripherals
AHB-Lite Advanced High-performance Bus (AHB) Interconnect for Cortex-M Processors and Peripherals via Advanced Peripheral Bus (APB) Bridge Interface
Altera
AMBA
AMBA Advanced Peripheral Bus Protocol
ampifiers
amplifiers
AN
analog and mixed-signal full-chip verification
analog and RF block-level development with flexible and reliable abstraction
Analog Circuit Design Volume 2
Analog Circuit Design Volume Three
analog devices
Analog-to-digital converter;energy efficient;low power;successive approximation register
and AMBA 4 AXI User Guide
and an example of a practical design is given.
and biasing for optimum temperature performance. The performance of the monolithic circuit
and controlling off-chip devices. Components available in Platform Designer incorporate these standard interfaces.
and CP1 with RF simulator
and decimation filters.
and detection applications.
and fabrication considerations for high-density integrated circuits in nanometer CMOS processes
and it analyzes circuit architectures that are suitable for analog building blocks. Highlighting various design challenges
and Makers
and Nichols
and optimizing Nios II processor-based embedded systems using Intel provided tools.
and parameters of the Triple-Speed Ethernet Intel FPGA IPcore. The Triple-Speed Ethernet Intel FPGA IP core is a configurable intellectual property (IP) core that incorporates a 10/100/1000-Mbps Ethernet media access controller (MAC) and an optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded PMA built with either on-chip transceiver I/Os or LVDS I/Os.
and recommends design styles and practices for developing
and state space variable method. Presentations are limited to linear
and the instruction set.
and using the waveform viewer to analyze and debug a design. Documents behavioral simulation of an RTL design as well as functional and timing simulation of synthesized and implemented designs.
and Virtex-7 FPGAs. Can be configured as tx or rx. Supports sharing GTX/ GTH transceiver between a transmitter and receiver.
APB
application and analysis of computational ideas and methods.
Application Notes
Application Reports
Applications
architectural exploration
area-efficient high-performance FIR filters utilizing either Multiply-Accumulate (MAC) or Distributed Arithmetic (DA) architectures.
ARM
ARM AMBA 5 AHB Protocol Specification AHB5
Arria 10
Artech House
Artix
Artix 7
Artix-7
Artix7
as amended by IEEE Stds
as measured at the MAC data SAP.
as part of the Vivado Design Suite
ASB
assertions
Asynchronous integral control
ATLANTIS PRESS
attachment unit interface
AUI
Auto-Negotiation
automation control
Avalon Cores
Avalon Memory-Mapped
Avalon Streaming
Avalon Tri-state Conduit Component
Avalon-TC
AXI
AXI BAR
AXI Interconnect
AXI Peripherals
AXI3
AXI4
AXI4-Lite
AXI4-Stream
Backplane Ethernet
Bandwidth
Bandwidth enhancement
beamforming
behavioral
benemale
BFM
bidirectional pins
bingdian001.com
Bode–Fano
Booting Methods
bridge
broadband
broadband amplifier
brush–commutator DC machines
buck converter
Buffer circuits
Bus functional model
C1WCD6VZebYu*DsiffI97^LlEcL*MyZbDj$JnPs$GdjZDFRZ9JY8hbZeugZ0
Cache and Memory Interface
Cambridge University Press
Casex Statements
Catalog
Changes and additions to IEEE Std 802.11
Charge pump (CP);delta&#8211;sigma;dynamic mismatch;dynamic mismatch corner frequency;flicker noise;flicker noise corner frequency;fractional-N frequency synthesizer (Frac-N);frequency synthesizer;gain mismatch;gain mismatch corner frequency;phase frequency detector (PFD);phase noise;reset delay mismatch;rms phase error;spurs;thermal noise;voltage-controlled oscillator (VCO)
Charge pump (CP);fractional-<formula formulatype="inline"><tex Notation="TeX">$N$</tex> </formula> phase-locked loops (PLLs);phase noise
chopper-stabilized amplifiers
Choppers;CMOS analog integrated circuits;operational amplifiers
Chopping
Circuit
Circuit modeling
circuit simulation platform
Circuit Simulations
Circuits
CIRCUITS AND DEVICES
clock
CMOS
CMOS bandgap reference
CMOS integrated circuits
CMOS; CGWO; optimization technique; operational amplifier; aspect ratio; power dissipation
COM051360 - COMPUTERS / Programming Languages / Python
COM070000 - COMPUTERS / User Interfaces
COM087020 - COMPUTERS / Desktop Applications / Design and Graphics
Combinational Circuits
combiner
Compact Models for Circuit Simulation
compiler
Component Editor
components
Compositor: Windfall Software
compression point
Computational electromagnetic
Computer Organization and Design: The Hardware/Software Interface
Computer-aided circuit analysis
Computing
Conditional Operator
conduit
Control loops
CORDIC
CORE Generator
core-clocking
Coregen
cores
correlated double sampling
corruption semantics
Cortex-M
CP1
crystal oscillators
current amplifier
Current mirror
curvature correction
Cyclone 10
cyclostationary noise
D/A Converters
data processing
Data Sheet
dc–dc buck converter
debug
debugging
December 2022
Describes the GTX/GTH transceivers in the 7 series devices.
Describes using the Vivado® simulator as both a stand-alone tool
design
design and verification
design cycle
design guidelines are suggested and test results are presented.
design intent
design methods
DesignWare Foundation Cores
DesignWare Synthesizable Components for AMBA 3 AXI
Device Technology
Devices & Systems
Digital beamforming (DBF)
Digital Logic
Digital Systems
direct digital synthesizer
discontinuous conduction mode (DCM)
distortion
Distributed Arithmetic
doc.type.documentation.ref
double clock time (DCT) control
ds249
DS534
DS558
ds768
ds814
DS843
DSM
DTE Power via the MDI
dual or quad SPI protocol.
dual-band
duplex
Dword
dynamic biasing
E-band
EDA应用技术
EDS
EE-Notes
EE247 Lecture Notes
eesof
electric machine circuit models
electric machines electromagnetics
Electromagnetics
Electronics Explained: Fundamentals for Engineers
electrostatic discharge protection
Embedded System
End Point
endian
Endpoint
Energy Efficient Ethernet
EPoC
EPON
EPON Protocol over Coax
Equality Operators
eSPI Core
Ethernet
Ethernet in the First Mile
Ethernet passive optical network
EURASIP Journal on Wireless Communications and Networking
evm
executable
express traffic
families
Fast Ethernet
fifth-generation (5G) communication
Figure-of-merit
filtering
FinFET
FinFET Device Operation
FinFET Device Technology
finite element analysis
FIR
First Edition (2013)
First Edition (2014) 1109pp 978-0-12-800001-4
flux orientation control
FM
FoM
FoMA
FPGA
Fractional spur
Frequency response
frequency response methods of analysis including Bode
frequency synthesis
functional
functional specification
gain and frequency response parameters
Gen 1/2/3 configurations.
Gen1
Gen2
Gen3
generic tri-state controller
Gigabit Ethernet
gm/ID methodology
graphical
gth
gtx
gty
HanWang PDF Technology
Hard IP for PCI Express Endpoint and Root Port
hi-Z
high efficiency
high throughput
high throughput; MAC; medium access control; MIMO; MIMO-OFDM; "multiple input
high-Z
hybrid biasing
Hybrid system
IEEE 1801™
IEEE 802.11ac™
IEEE 802.3
IEEE 802.3™
IEEE Circuits and Systems Magazine;2014;14;2;10.1109/MCAS.2014.2314263
IEEE Custom Integrated Circuits Conference 2006;2006; ; ;10.1109/CICC.2006.320979
IEEE International Sympoisum on Circuits and Systems;1991; ; ;10.1109/ISCAS.1991.176049
IEEE Journal of Solid-State Circuits;1990;25;6;10.1109/4.62165
IEEE Journal of Solid-State Circuits;1993;28;12;10.1109/4.262000
IEEE Journal of Solid-State Circuits;2000;35;3;10.1109/4.826814
IEEE Journal of Solid-State Circuits;2001;36;3;10.1109/4.910480
IEEE Journal of Solid-State Circuits;2002;37;11;10.1109/JSSC.2002.803936
IEEE Journal of Solid-State Circuits;2002;37;8;10.1109/JSSC.2002.800925
IEEE Journal of Solid-State Circuits;2006;41;12;10.1109/JSSC.2006.884195
IEEE Journal of Solid-State Circuits;2010;45;4;10.1109/JSSC.2010.2042254
IEEE Microwave Magazine;2010;11;1;10.1109/MMM.2009.935203
IEEE Microwave Magazine;2019;20;5;10.1109/MMM.2019.2898022
IEEE Solid-State Circuits Magazine;2016;8;2;10.1109/MSSC.2016.2543061
IEEE Solid-State Circuits Magazine;2018;10;2;10.1109/MSSC.2018.2822859
IEEE Transactions on Circuits and Systems I: Regular Papers;2005;52;2;10.1109/TCSI.2004.841594
IEEE Transactions on Circuits and Systems I: Regular Papers;2010;57;8;10.1109/TCSI.2009.2039832
IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing;2001;48;4;10.1109/82.933799
implementation
in
Inc.
increased productivity and throughput
induction machines transients
inductor
Inequality Operators
information exchange
Input resistance
Input Return Loss
Institution of Engineering
Integrated circuits
intercept point
intercept points
Interconnect
interface specification
Internal
Internally compensated CMOS op amps have been widely used in sampled-analog signal processing applications over the past several years. However
Internet of things (IoT)
interoperability
interpolation
IP
IP core
IP integrator
IP reuse
IP Version: 19.3.0. Describes the features
IP2
IP3
is reported.
ISBN 978-7-03-022031-8
ISBN-10:
ISBN-13:
ISBN-13: 978-7-5605-1884-2
ISBN-13: 9780387961316
ISBN-13: 9780470167588
ISBN-13: 9789814291651
ISBN: 0135309247; Date: May 22
ISBN: 7115150559
ISBN：9787121096075
ISBN：9787302211464
isolation
JEDEC
jitter
jitter extraction
JTAG Debug Module
K 7
K-7
K7
Keywords
Keywords- Advanced Design Systems
Kintex
Kintex 7
Kintex-7
Kintex7
L1 -gain performance
LAN
Laplace transforms and transfer functions
Leakage Currents
least squares and Monte Carlo methods. This book balances the development
level shifting
Linear and switching power
Linear integrated circuits
Linear Matrix Inequalities
linker
LMI technique
load-pull
local area network
LogiCORE
loss
low <italic xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">IQ</italic> low dropout (LDO)
Low Noise Amplifier
Low voltage circuits
low-noise amplifier (LNA)
MAC
management
masking
massive multiple-input multiple-output (MIMO)
master bridge
MATERIALS
MATLAB
matlab 80
MATLAB exercises for robust and optimal control
MATLAB for Control System Engineers is designed as an introductory undergraduate or graduate course for science and engineering students of all disciplines. Control systems engineering is a multidisciplinary subject and presents a control engineering methodology based on mathematical fundamentals and stresses physical system modeling. The classical methods of control systems engineering are covered here using MATLAB software: matrix analysis
McGraw-Hill
MDI
media independent interface
medium dependent interface
memory bus design
Memory control
memory map
MEMS
Metal-Oxide-Semiconductor
Method
MIB
Micorsystems
micromechanical resonator
microprocessors
MII
millimeter-wave
millimeter-wave (mm-Wave)
MNL-AVABUSREF
mode selection
model reduction
Moderate inversion
Moments
monitor
Monolithic integrated circuits
MPMC
mSGDMA
multi-feed antenna
multi-point MAC control
multi-port
multi-user MIMO
multibeam system
multiple output
Multiple-Gate
multiplication factor
Multiply-Accumulate
Networks
networksynthesis
NimoDoc
Nios II
Nios II Debug
Nios II Processor Core
NMOS LDO
noise
noise cancellation
Noise Figure
noise shaping
Non-Blocking Assignments
noncontiguous frequency segments
none
numerical integration and differentiation
Nyquist
OCR-PDF
of
on-demand buffer
opamp
Opamp design
Operational amplifiers
optimal control
optimal electromagnetic design
oscillator
oscillator phase noise
Output resistance
Output Return Loss
Parasitic Elements
PCI Express
PCIe
PCS
PDF Attachment
PDF Creator
pdflib
PDFￗﾪﾻﾻￆ
Perl语言入门 第六版
PG153
phase and gain margin and bandwidth
phase dithering
phase generator
phase noise
phase to SIN/COS
phase-error correction
phase-locked loop (PLL)
PHY
physical coding sublayer
Physical Layer
physical medium attachment
physical medium dependent
piezoelectric resonator
pin-out flow
Platform Designer
PLL
PMA
PMD
PoDL
pole-zero analysis
Poles and zeros
power amplifier (PA)
power amplifiers (PAs).
power domains
Power engineering
power intent
power modes
Power over Data Lines
Power over Ethernet
power states
power-aware design
Predicting IP2
Principles of Sigma-Delta Modulation for Analog-to-Digital Converters
product.id.P10089
product.id.P10099
product.id.P10101
product.id.P10115
product.id.P10119
product.id.P10122
product.id.P11426
product.id.P11427
product.id.P11481
product.id.P11493
product.version.10.3c
product.version.v2020.1
Programming Model
progressive design refinement
Project Navigator
Proportional control
propulsion control
Publisher:
Publisher: O'Reilly Media
pulse-width-modulation (PWM) current mode control
Python
QSPI Controller Core
Qsys
quad
Quad SPI
Quartus Prime
radio frequency
Radio Frequency System Architecture and Design
reading and writing registers and memory
reconciliation sublayer
reference
Reference circuits
Reference interface specification PDF documentation for the AMBA AXI Protocol
Reference interface specification PDF documention for the AMBA4 AXI4-Stream Protocol
reference spur
Referex
Referex; Computer Science (General);Information Systems;Electrical and Electronic Engineering;
relaxation oscillator
repeater
retention
retention strategies
RF design
RF Simulation
rfic
Ring PLL
ring voltage-controlled oscillator (VCO)
robust and optimal control
robust control
robust control textbook
room temperature trim
root finding
root locus
root locus analysis and design
Root Port
rotational
RS
S 3
S 6
S-3
S-6
S3
S6
sample-reset loop filter
sampling noise
SBAA328
scaling
Scientific Computing; Taylor’s Theorem; Roundoff Errors; Error Propagation; Linear Systems; Root Finding; Interpolation; Numerical Integration; Numerical Differentiation; Initial Value Problems; Boundary Value Problems; Iterative Methods; Least Squares Problems; Monte Carlo Methods; Parallel Computing; MATLAB
Second Edition (2018) 408pp. 978-0-12-811641-8
second order systems approximations
Semiconductor
Semiconductor Physics
serdes
Serial Flash Controller Core
SiGe
sigma-delta adc topology
signal acquisition
signals
Simulation
simulator
slave bridge
Small Geometry FinFETs
SoC
some will apply specifically to our case in question.
Spartan
SpectreRF
speed control
SPI
SPI Core
Springer
Springer 2011
SSC
state-space techniques
Subject
surface PM synchronous machines
suspension control
sustaining amplifier
switched-capacitor
switched-capacitor tracking compensation
switched-loop filter (SLF)
SWRS040
SWRS040C
synchronous machine transients
system design
TEAM DDU
technical article
Technicians
TeX output 2014.03.17:1515
that features three low phase-noise VCOs with a fundamental frequency range of 3.0 GHz to 6.0 GHz and a programmable dual RF output divider stage which allows coverage from 46.875 MHz to 6 GHz.
The
the application to circuits with higher output voltage is simplified. Incorporation of the new two-transistor cell in a three-terminal 2.5-V monolithic reference is described. The complete circuit is outlined in functional detail together with analytical methods used in the design. The analytical results include sensitivity coefficients
The AXI Memory Mapped to PCI Express™ core is an interface between the AXI4 and PCI Express.
The AXI Quad SPI core connects the AXI4 interface to SPI slave devices which support the standard
The book presents design methods for analog integrated circuits with improved electrical performance. It describes different equivalent transistor models
The DDS (Direct Digital Synthesizer) Compiler core sources sinusoidal waveforms for use in many applications. A DDS consists of a Phase Generator and a SIN/COS Lookup Table.
The effects of pole-zero pairs (doublets) on the frequency response and settling time of operational amplifiers are explored using analytical techniques and computer simulation. It is shown that doublets which produce only minor changes in circuit frequency response can produce major changes in settling time. The importance of doublet spacing and frequency are examined. It is shown that settling time always improves as doublet spacing is reduced whereas the effect of doublet frequency is different for 0.1 and 0.01 percent error bands. Finally it is shown that simple analytical formulas can be used to estimate the influence of frequency doublets on amplifier settling time.
The numerous worked examples (over 400 problems and solutions) are intended to provide the reader with an awareness of the general applicability of control theory using MATLAB. An extensive bibliography to guide the students to further sources of information on control systems engineering using MATLAB is provided at the end of the book.
the other for buffer applications requiring wide common-mode input range. Small signal analysis is developed for the open-loop and PSRR responses of the two amplifiers. In addition
the popular two-stage op amp suffers from poor AC power supply rejection to one of the power rails. Two circuits are presented that overcome the power-supply rejection ratio (PSRR) problems of the earlier amplifier: one for virtual ground applications such as switched-capacitor integrators
the programming model
The specific processor that we analyze here is ADSP-TS201S from TigerSHARC® family of processors. Some of the subjects discussed here will apply to jitter in general
The STW81200 is a dual architecture frequency synthesizer (Fractional-N and Integer-N)
the text offers a complete understanding of architectural- and transistor-level design issues of analog integrated circuits. It examines important trends in the design of high-speed and power-efficient front-end analog circuits that can be used for signal conditioning
The Xilinx LogiCORE IP CORDIC core implements a generalized coordinate rotational digital computer (CORDIC) algorithm.
The Xilinx LogiCORE IP FIR Compiler core provides a common interface for users to generate highly parameterizable
Theory of Modeling and Simulation
Third Edition
Third Edition (2019) i-iii. doi:10.1016/B978-0-12-813370-5.00002-X
This amendment defines modifications to both the IEEE 802.11 PHY and MAC sublayer so that modes of operation can be enabled that are capable of much higher throughputs
This application note and accompanying source code shows designers how to create a very small PCIe to AXI bridge which supports 1 DWORD reads and writes from the host to the FPGA Endpoint
This core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.
This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices
This document describes how to most effectively use the Nios II Embedded Design Suite (EDS) tools
This IP core is used for building a PCI Express® Media Access Controller (MAC) layer. It supports 1/2/4/8/16-lane
This textbook covers essential numerical techniques including basic methods for linear systems
This user guide describes the embedded peripherals IP cores that work seamlessly with the Nios II processor.
TigerSHARC
Time series analysis
time-invariant continuous systems.
timing
topologies
topology
Training Kit
trans impedance amplifier
transceiver
transistor
translation
tri-state conduit
Triple-Speed Ethernet
tristate conduit
Tutorial
type field
UG-01073
ug476
ug774
ultra-low-quiescent current
ultralow-quiescent current
UltraScale
UltraScale architecture
ultrascale plus
UltraScale+
Updated for Intel Quartus Prime Design Suite: 18.1. Avalon interfaces simplify system design by allowing you to easily connect components in Intel FPGAs. The Avalon interface family defines interfaces appropriate for streaming high-speed data
Updated for Intel Quartus Prime Design Suite: 19.3
Updated for Intel Quartus Prime Design Suite: 19.4. This document provides information about the Nios II processor architecture
USB 2.0
USB 2.0 规范初探
User Guide
using a fraction of the resources of the fully featured AXI Memory Mapped to PCIe Gen2 bridge.
V 4
V 5
V 6
V 7
V-4
V-5
V-6
V-7
V4
V5
V6
V7
verification
Verification Academy - UVM Cookbook
verify
Verilog
Version N-2017.12-SP2
Version U-2022.12
very
VHDL
Virtex
Virtex 7
Virtex-7
Virtex7
Vivado
Vivado Design Suite
VLAN tag
voltage-controlled oscillator
voltage-domain models
We will explain how IP3 is generated and how its values are linked. Learn how IP3 and intermodulation are generated and why they are important.
Week inversion
which includes temperature coefficients of 5 ppm//spl deg/C over the military temperature range
wide load current range
wider bandwidth
Wiley
Wiley-IEEE Press
wireless
wireless communication
WISHBONE System-on-Chip (SoC)Interconnection Architecturefor Portable IP Cores
with a maximum throughput of at least 100 Mb/s
www.ebook3000.com
www.it-ebooks.info
XA
XDC
Xilinx大学合作计划指定教材
XSim
Y-factor
zc706
ZHCC347
ZHCP055
zyng
Zynq
Zynq-7000
【ISBN号】978-7-121-10991-1
【丛书名】国外电子与通信教材系列
【中图法分类号】TP3
【出版商】 北京市：电子工业出版社
【页 数】 319
一本开源指令集的指南
上架时间：2010-3-19
丛书名: 图解实用电子技术丛书
丛书名： 微电子与集成电路技术丛书
人民邮电出版社
作者： 魏廷存
关键字
冯新宇著.ADS射频电路设计与仿真入门及应用实例.北京：电子工业出版社
出版日期：2010 年3月
出版社: 人民邮电出版社
出版社: 科学出版社有限责任公司
出版社：清华大学出版社
动态系统-反馈控制
化工
北京航空航天大学出版社
同济大学数学系编.高等数学 第7版 上.北京：高等教育出版社
国外电子与通信教材系列
国外电子与通信教材系列; 电子工业出版社; 2009年; 383页
国家集成电路工程领域工程硕士系列教材
图形学
图灵电子与电气工程丛书
实用教程
射频电路-电路设计-计算机辅助设计-软件包
平装: 296页
平装: 620页
建筑
开本: 16开
开本：16开
微波技术 微波技术
控制之美 卷2
控制系统-高等学校-教材
数字信号处理
数字电子技术基础
数字电路－电路设计
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普通高等教育“十一五”国家级规划教材
曹丽娜，樊昌信编著.通信原理 第7版 学习辅导与考研指导.北京市：国防工业出版社
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模拟电路-电子技术-高等学校-教材
模拟集成电路-电路设计-高等学校-教材
清华大学信息科学技术学院教材——微电子光电子系列
清华大学出版社
清华搬双语教学用书
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科学出版社; 国家集成电路工程领域工程硕士系列教材; 2008年; 301页
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阔永红.数字信号处理 时域离散随机信号处理.西安：西安电子科技大学出版社
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（美）C.RichardJohnson著.软件无线电.北京市：机械工业出版社
（美）亚历山大著.电路基础 第5版.北京：机械工业出版社
（美）吉恩 F.富兰克林（Gene F.Franklin），（美）J.大卫·鲍威尔（J.David Powell），（美）阿巴斯·埃马米·纳尼（Abbas Emami.Naeini）著.动态系统的反馈控制[M].北京：机械工业出版社
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（英）DouglasSelf著.音频功率放大器设计手册.北京市：人民邮电出版社
（英）监凯维奇，（美）泰勒著.有限元方法 基本原理 第1卷.北京市：清华大学出版社
（韩）赵勇洙等著；孙锴，黄威译.MIMO OFDM无线通信技术及MATLAB实现.北京市：电子工业出版社
ￂￖￌ￢
Series
Exclude Series
Shelves
ADC与DAC 数据转换器
EDA开发技术
FPGA
IO ESD
SOC
SPICE仿真器原理
linux
verilog
优化理论 OPTIM
低噪放LNA
信号系统与无线收发机signal wireless
光传输
功率放大器PA
半导体工艺 PDK model TCAD
噪声分析 noise
图像处理
射频.微波 RF MW
开关电源 线性稳压源 带隙基准源 电源管理 DCDC ACDC LDO BGR PM
微积分 微分方程 diffEq
总线与接口 bus
振荡器OSC 压控振荡器VCO
控制系统 稳定性 补偿
数值分析 numerical analysis
数字IC后端
数字IC设计
数字IC验证
数字信号处理
有限元 FEM
概率与统计
模拟IC教材
模拟电路优化 gmid
比较器 comparator
波形分析与测量 wave analysis
混频器 mixer
滤波器 filter
版图设计 layout
电磁场与电磁波 EM
电荷泵 CP
电路基础 basic ciruit
科学计算及MATLAB
线性代数linear algebra
谐波平衡 HB
运放 开关电容 OPAMP SC
锁相环 PLL DLL
静态时序分析 STA
音频处理
Exclude Shelves
ADC与DAC 数据转换器
EDA开发技术
FPGA
IO ESD
SOC
SPICE仿真器原理
linux
verilog
优化理论 OPTIM
低噪放LNA
信号系统与无线收发机signal wireless
光传输
功率放大器PA
半导体工艺 PDK model TCAD
噪声分析 noise
图像处理
射频.微波 RF MW
开关电源 线性稳压源 带隙基准源 电源管理 DCDC ACDC LDO BGR PM
微积分 微分方程 diffEq
总线与接口 bus
振荡器OSC 压控振荡器VCO
控制系统 稳定性 补偿
数值分析 numerical analysis
数字IC后端
数字IC设计
数字IC验证
数字信号处理
有限元 FEM
概率与统计
模拟IC教材
模拟电路优化 gmid
比较器 comparator
波形分析与测量 wave analysis
混频器 mixer
滤波器 filter
版图设计 layout
电磁场与电磁波 EM
电荷泵 CP
电路基础 basic ciruit
科学计算及MATLAB
线性代数linear algebra
谐波平衡 HB
运放 开关电容 OPAMP SC
锁相环 PLL DLL
静态时序分析 STA
音频处理
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Chinese
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