Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs

Rakesh H. Patel & William Bereza

DOI

IEEE Custom Integrated Circuits Conference 2006;2006; ; ;10.1109/CICC.2006.320979

Publisher: IEEE

Description:

IEEE Custom Integrated Circuits Conference 2006;2006; ; ;10.1109/CICC.2006.320979