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A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly

PCIe Ring PLL SSC SoC adaptive clock core-clocking microprocessors sample-reset loop filter

Publisher: IEEE

Description:

IEEE Transactions on Circuits and Systems I: Regular Papers;2018;65;7;10.1109/TCSI.2017.2784319