7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge (XAPP1286)
AXI AXI4-Lite AXI BAR Dword Endpoint PCIe This application note and accompanying source code shows designers how to create a very small PCIe to AXI bridge which supports 1 DWORD reads and writes from the host to the FPGA Endpoint endian masking reference translation using a fraction of the resources of the fully featured AXI Memory Mapped to PCIe Gen2 bridge. zc706
Published: Feb 18, 2009
Description:
This application note and accompanying source code shows designers how to create a very small PCIe to AXI bridge which supports 1 DWORD reads and writes from the host to the FPGA Endpoint, using a fraction of the resources of the fully featured AXI Memory Mapped to PCIe Gen2 bridge.