Xilinx, Inc.
Gen1 Gen2 Gen3 Gen 1/2/3 configurations. MAC PCIe PHY This IP core is used for building a PCI Express® Media Access Controller (MAC) layer. It supports 1/2/4/8/16-lane UltraScale UltraScale architecture UltraScale+ Vivado families gth gty ultrascale plus
Published: May 17, 2019
Description:
This IP core is used for building a PCI Express® Media Access Controller (MAC) layer. It supports 1/2/4/8/16-lane, Gen 1/2/3 configurations.