理工书库 lilin | Triple-Speed Ethernet Intel® FPGA IP User Guide

Triple-Speed Ethernet Intel® FPGA IP User Guide

Language: Chinese

FPGA IEEE 802.3 IP Version: 19.3.0. Describes the features IP core MAC PCS Triple-Speed Ethernet Updated for Intel Quartus Prime Design Suite: 19.3 and parameters of the Triple-Speed Ethernet Intel FPGA IPcore. The Triple-Speed Ethernet Intel FPGA IP core is a configurable intellectual property (IP) core that incorporates a 10/100/1000-Mbps Ethernet media access controller (MAC) and an optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded PMA built with either on-chip transceiver I/Os or LVDS I/Os. signals

Description:

Updated for Intel Quartus Prime Design Suite: 19.3, IP Version: 19.3.0. Describes the features, signals, and parameters of the Triple-Speed Ethernet Intel FPGA IPcore. The Triple-Speed Ethernet Intel FPGA IP core is a configurable intellectual property (IP) core that incorporates a 10/100/1000-Mbps Ethernet media access controller (MAC) and an optional 1000BASE-X/SGMII physical coding sublayer (PCS) with an embedded PMA built with either on-chip transceiver I/Os or LVDS I/Os.