JESD204 v7.2 LogiCORE IP Product Guide (PG066)

Xilinx, Inc.

Language: Chinese

Published: Aug 18, 2017

Description:

This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices, Kintex-7, and Virtex-7 FPGAs. Can be configured as tx or rx. Supports sharing GTX/ GTH transceiver between a transmitter and receiver.