Standard Verification Rule Format (SVRF) Manual 2023
Siemens Industry Software
Advanced Analog Building Blocks
Shen
Fundamentals of Layout Design for Electronic Circuits
Jens Lienig Juergen Scheible
Advanced Opamp Topologies (Part II)
Michael H. Perrott
Cadence SKILL Lan guage Reference
Inc. Cadence Design Sys tems
一种基于广义时间和传递常数的快速分析法 郑立博
CNKI
Avalon Verification IP Suite User Guide
Altera Corporation
Session 9: ML Processors From Cloud to Edge
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模拟集成电路与系统 Analog Integrated Circuits and Systems
池保勇 编著
模拟集成电路设计精粹——Analog Design Essentials
Willy M.C. Sansen 著 & 陈莹梅 译 & 王志功 审校
IEEE Std 802.11g-2003 [Amendment to IEEE Std 802.11, 1999 Edition ...
LAN/MAN Standards Committee of the IEEE Computer Society
综合与Design Compiler
阳晔
AMPLIFIER ARCHITECTURE AND APPLICATION THEREOF TO A BAND-GAP ...
High Performance SAR-based ADC Design in Deep Sub-micron CMOS
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半导体物理与器件 （第三版）
（美）尼曼著 赵毅强 姚素英 解晓东等译
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
ISSCC2021 Session 27
ISSCC2021 Session 29
Session 30: Non-Volatile Memories
Session 31: Analog Techniques
Session 32: Frequency Synthesizers
Session 33: High-Voltage, GaN and Wireless Power
Session 34: Emerging Imaging Solutions
Session 36: Hardware Security
Session 35: Adaptive Digital Techniques for Variation Tolerant ...
ISSC2021 SESSION 2
Presentation
Gaurav Singh
ISSCC2021-1 3
Microsoft PowerPoint - plenary_2021_reserve
Albert
Session 4
Session 3
Session 5
Session 7
Session 6
Session 8
Session 9
Session 10
Session 11V-ADVANCED WIRELINE LINKS AND TECHNIQUES
Session 12
Session 13
Session 15
Session 16
Session 17
Session 18
Session 19
Session 20
Session 21
Session 22
Session 23
Session 24
Session 25
Session 27
Session 30
Session 26V
Session 28V
Session 29V
Session 31
Session 32
Session 33
Session 34
Session 35
Session 36
Session 1: Plenary Session — Invited Papers
Session 4: Processors
Session 3: Highlighted Chip Releases: Modern Digital SoCs
Session 2: Highlighted Chip Releases: 5G and Radar Systems
ISSCC2021-SC3-Clo[..] Clock Distribution, and Clock Management ...
ISSCC2021-SC4-Pro[..] Clock Generation, Distribution, and Clock ...
ISSCC2021-T1-Fund[..] of RF and Mm-Wave Power Amplifier Designs
ISSCC2021-T2-Fund[..] of Memory Subsystem Design for HPC and ...
ISSCC2021-T4-Meas[..] and Evaluating the Security Level of ...
ISSCC2021-T5-Cali[..] Techniques in ADCs
ISSCC2021-T3-Silicon Photonics – from Basics to ASICs
ISSCC2021-T6-Basics of DAC-based Wireline Transmitters
ISSCC2021-T7-Basic Design Approaches to Accelerating Deep Neural ...
ISSCC2021-T8-On-Chip Interconnects Basic Concepts, Designs, ...
ISSCC2021-T11-Ult[..] Power Wireless Receiver Design