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Wishbone B4

Wishbone B4

ISSCC2021-1 3

ISSCC2021-1 3

Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC) (Sridhar Gangadharan, Sanjay Churiwala (auth.)) (z-lib.org)

Constraining Designs for Synthesis and Timing Analysis A Practical ...

PrimeWave� Design Environment User Guide

PrimeWave� Design Environment User Guide

CMOS射频集成电路分析与设计 (池保勇, 余志平, 石秉学) (z-lib.org)

CMOS射频集成电路分析与设计 (池保勇, 余志平, 石秉学) (z-lib.org)

Elementary Differential Equations and Boundary Value Problems

Elementary Differential Equations and Boundary Value Problems

William E. Boyce & Richard C. Diprima & Douglas B. Meade

Cancellation of Amplifier Offset and f-Noise An Improved Chopper Stabilized Technique

Cancellation of Amplifier Offset and f-Noise An Improved Chopper ...

数值分析

数值分析

Accurate and Rapid Measurement of IP2 and IP3

Accurate and Rapid Measurement of IP2 and IP3

A compact power-efficient 3 V CMOS rail-to-rail input/output operational amplifier for VLSI cell lib - Solid-State Circuits, IEEE Journal of

A compact power-efficient 3 V CMOS rail-to-rail input/output ...

verilog HDL那些事

verilog HDL那些事

DesignWare Synthesizable Components for AMBA 3 AXI, and AMBA 4 AXI User Guide, Version 2020.03a

DesignWare Synthesizable Components for AMBA 3 AXI, and AMBA ...

Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design

Keliu Shu-2005 CMOS PLL Synthesizers Analysis and Design

Report for current mirror OPAMP

Report for current mirror OPAMP

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...

Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...

Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly

Session 11V-ADVANCED WIRELINE LINKS AND TECHNIQUES

Session 11V-ADVANCED WIRELINE LINKS AND TECHNIQUES

Harmonic Balance for Nonlinear Vibration Problems

Harmonic Balance for Nonlinear Vibration Problems

Books

CN101140511B-硅谷数模2010-Cascaded carry binary adder

CN101140511B-硅谷数模[..] carry binary adder

CN101969305B-威盛电子2012-Potential conversion circuit

CN101969305B-威盛电子[..] conversion circuit

CN106656160A-上海集成电路研发中心2017-优化占空比的高速电平转换电路

CN106656160A-上海集成[..]

ELKHOLY-DISSERTATION-2016-adpll

ELKHOLY-DISSERTAT[..]

HJ-MASH 多模多标准CMOS锁相环频率综合器中小数分频器的设计史鹏鹏

HJ-MASH 多模多标准CMOS锁相环频率综合器[..] 史鹏鹏

Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N PLLs

Noise and Spur Comparison of Delta-Sigma Modulators in Fractional-N ...

Bo Zhou & Yao Li & Fuyuan Zhao

Scaling <formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...

Shih-An Yu & Peter R. Kinget

The Delta-Sigma Modulator [A Circuit for All Seasons]

The Delta-Sigma Modulator [A Circuit for All Seasons]

学校代码： 10246

学校代码： 10246

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

Analog Behavioral Modeling with the Verilog-A Language

Analog Behavioral Modeling with the Verilog-A Language

基准电压源和线性稳压器的设计-tangzhangwen

基准电压源和线性稳压器的设计-ta[..]

基准源和温度检测模块设计-tangzhangwen

基准源和温度检测模块设计-tang[..]

CMOS 带隙基准源研究-tangzhangwen

CMOS 带隙基准源研究-tangzhangwen

全差分运算放大器设计-tangzhangwen

全差分运算放大器设计-tangzh[..]

OPAMP设计-tangzhangwen

OPAMP设计-tangzhangwen

LDO设计-tangzhangwen

LDO设计-tangzhangwen

二级密勒补偿运算放大器

二级密勒补偿运算放大器

Michiel Steyaert CMOS CELLULAR RECEIVER FRONT-ENDS

Michiel Steyaert CMOS CELLULAR RECEIVER FRONT-ENDS

相位噪声、通行链路预算

相位噪声、通行链路预算

Understanding Phase Noise in LC VCOs

Understanding Phase Noise in LC VCOs

A Key Problem in RF Integrated Circuits

S_Para_E.PM6

S_Para_E.PM6

Pages from M.E. Van Valkenburg - Network Analysis 6(1959, Prentice Hall, Inc)

Pages from M.E. Van Valkenburg - Network Analysis 6(1959, Prentice ...

PoleZero.dvi

PoleZero.dvi

Dynamic Response of Linear Systems Impact of Pole & Zero Locations

Dynamic Response of Linear Systems Impact of Pole & Zero Locations

功率谱密度计算

功率谱密度计算

ADI 技术指南合集

ADI 技术指南合集

德州仪器高性能模拟器件高效应用指南之数据转换器_TI 大学计划

德州仪器高性能模拟器件高效应用指南[..] 大学计划

Texas Instruments, Incorporated [ZHCP055,*]

芯片I／O缓冲及ESD电路设计

芯片I／O缓冲及ESD电路设计

eetop.cn Matching

eetop.cn Matching

ESD in Silicon Integrated Circuits

ESD in Silicon Integrated Circuits

柯明道ESD简洁版

柯明道ESD简洁版

Virtuoso Editing 的使用简介

Virtuoso Editing 的使用简介

基于CMOS工艺的全芯片ESD保护电路设计

基于CMOS工艺的全芯片ESD保护[..]

esd-circuits-and-devices

esd-circuits-and-[..]

A mixed-mode esd protection circuit simulation-design methodology - Solid-State Circuits, IEEE Journal of

A mixed-mode esd protection circuit simulation-design methodology ...

CMOS电路芯片ESD保护电路设计技术的发展赵近

CMOS电路芯片ESD保护电路设计[..] 赵近

Abraham uta GPIO ESD

Abraham uta GPIO ESD

ESD Design and Synthesis (1)

ESD Design and Synthesis (1)

CN104601160B-灿芯半导体2017-带ESD的高速输出级

CN104601160B-灿芯半导[..]

FPGA 全芯片 ESD 防护设计和优化

FPGA 全芯片 ESD 防护设计和优化

DDR3存储器接口电路的设计与实现-ESD写得好

DDR3存储器接口电路的设计与实现[..]

模拟集成电路设计与仿真-何乐年

模拟集成电路设计与仿真-何乐年

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller Compensation

Design Procedures for Three-Stage CMOS OTAs With Nested-Miller ...

Power supply rejection ratio in operational transconductance amplifiers - Circuits and Systems, IEEE Transactions on

Power supply rejection ratio in operational transconductance ...

CMOS高性能运算放大器研究与设计

CMOS高性能运算放大器研究与设计

Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range

Design techniques for cascoded CMOS op amps with improved PSRR ...

D.B. Ribner & M.A. Copeland

NoiseDesign.dvi

NoiseDesign.dvi

Advanced Opamp Topologies (Part II)

Advanced Opamp Topologies (Part II)

Michael H. Perrott

MOSAmpNoise.dvi

MOSAmpNoise.dvi

MIPI高速数据接口的研究与实现

MIPI高速数据接口的研究与实现

Advanced Opamp Topologies

Advanced Opamp Topologies

Michael H. Perrott

A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI

A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI

A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current Pre-Amplifier for High Frequency Lateral MEMS Oscillators

A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...

Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi

Internal and external op-amp compensation: a control-centric tutorial - American Control Conference, 2004. Proceedings of the 2004

Internal and external op-amp compensation: a control-centric ...

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

K. Bult;G.J.G.M. Geelen

Distributed Loss-Compensation Techniques for Energy-Efficient Low-Latency On-Chip Communication

Distributed Loss-Compensation Techniques for Energy-Efficient ...

The Biquadratic Filter [A Circuit for All Seasons]

The Biquadratic Filter [A Circuit for All Seasons]

Relationship between frequency response and settling time of operational amplifiers

Relationship between frequency response and settling time of ...

B.Y.T. Kamath, R.G. Meyer & P.R. Gray

二级运放建立时间与相位裕度的分析与优化

二级运放建立时间与相位裕度的分析与优化