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多采样率系统：采样率转换和数字滤波器组

多采样率系统：采样率转换和数字滤波器组

Session 13

Session 13

Microsoft Word - AXI protocol 翻译.doc

Microsoft Word - AXI protocol 翻译.doc

A0130105

A0130105

一种具有温度补偿的带隙基准源及其输出缓冲器何捷

一种具有温度补偿的带隙基准源及其输[..] 何捷

Standard Verification Rule Format (SVRF) Manual 2023

Standard Verification Rule Format (SVRF) Manual 2023

Siemens Industry Software

一种加入动态补偿电路的快速响应LDO设计

一种加入动态补偿电路的快速响应LDO设计

ISSCC2021 Session 28

ISSCC2021 Session 28

Guillermo Gonzalez

Guillermo Gonzalez

Microwave Transistor Amplifiers Analysis & Design

High Efficiency RF and Microwave Solid State Power Amplifiers

High Efficiency RF and Microwave Solid State Power Amplifiers

Paolo Colantonio, Franco Giannini & Ernesto Limiti

深入理解LINUX虚拟内存管理

深入理解LINUX虚拟内存管理

（爱尔兰）MEL GORMAN著

Continuous-Time Sigma-Delta AD Conversion Fundamentals, Performance Limits and Robust Implementations by Friedel Gerfers, Maurits Ortmanns (z-lib.org)

Continuous-Time Sigma-Delta AD Conversion Fundamentals, Performance ...

半导体器件物理与工艺电子版第二版(cut)

半导体器件物理与工艺电子版第二版(cut)

补偿电路总结

补偿电路总结

DELAY LOCKLOOP CIRCUIT

DELAY LOCKLOOP CIRCUIT

一种用于LDO的低功耗带隙基准电压源

一种用于LDO的低功耗带隙基准电压源

无电容型LDO的研究现状与进展

无电容型LDO的研究现状与进展

Sampled Systems and the Effects of Clock Phase Noise and Jitter Application Note (AN-756)

Sampled Systems and the Effects of Clock Phase Noise and Jitter ...

Analog Devices, Inc.

Books

(Analog Circuits and Signal Processing) Danica Stefanovic, Maher Kayal

(Analog Circuits and Signal Processing) Danica Stefanovic, Maher ...

(EE) Razavi, Design of Analog CMOS Integrated Circuits 2nd

(EE) Razavi, Design of Analog CMOS Integrated Circuits 2nd

0-306-47052-7_BookFrontmatter_OnlinePDF.pdf

0-306-47052-7_Boo[..]

A 0.46ps RJ<inf>rms</inf> 5GHz wideband LC PLL for multi-protocol 10Gb/s SerDes

A 0.46ps RJ<inf>rms</inf> 5GHz wideband LC PLL for multi-protocol ...

Chethan Rao & Alvin Wang & Shaishav Desai

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin

0071509054.pdf

0071509054.pdf

0132642786.pdf

0132642786.pdf

Neil H. E. Weste

04_TechActive.fm

04_TechActive.fm

A 1 GHz CMOS RF Front-End IC for a Direct-Conversion Wireless Receiver - Solid-State Circuits, IEEE Journal of

A 1 GHz CMOS RF Front-End IC for a Direct-Conversion Wireless ...

A 1.24 μA Quiescent Current NMOS Low Dropout Regulator With Integrated Low-Power Oscillator- Driven Charge-Pump and Switched-Capacitor Pole Tracking Compensation

A 1.24 μA Quiescent Current NMOS Low Dropout Regulator With ...

Raveesh Magod & Bertan Bakkaloglu & Sanjeev Manandhar

A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier - Solid-State Circuits, IEEE Journal of

A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier - Solid-State Circuits, ...

1.5Bit 级pipelined+ADC典型单级电路结构实现研究

1.5Bit 级pipelined+ADC典型单[..]

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...

Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai

12bit pipeline ADC design

12bit pipeline ADC design

12位50Msps流水线A D转换器的研究与设计

12位50Msps流水线A D转换器的研究与设计

1498422645524829124-05963071

14984226455248291[..]

1499066564577362562-06963235

14990665645773625[..]

16位高速CMOS流水线模数转换器关键技术研究 (1)

16位高速CMOS流水线模数转换器[..] (1)

1V供电的低噪声带隙基准电压源

1V供电的低噪声带隙基准电压源

A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State Circuits, IEEE Journal of

A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State ...

2-Stage OTA Design

2-Stage OTA Design

A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage CMOS for FPGA applications

A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...

Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao

A 2.7-V 900-MHz CMOS LNA and Mixer - Solid-State Circuits, IEEE Journal of

A 2.7-V 900-MHz CMOS LNA and Mixer - Solid-State Circuits, IEEE ...

2.7Gbps收发器中LVDS驱动电路的设计

2.7Gbps收发器中LVDS驱动[..]

2002 Book On-ChipESDProtectionForIntegra

2002 Book On-ChipESDProtect[..]

2004Beek

2004Beek

2005 Book ClockGeneratorsForSOCProcessor

2005 Book ClockGeneratorsFo[..]

2010_FrontMatter_pgs001-005_stv

2010_FrontMatter_[..]

2014 PhD-Thesis BAG A Designer-Oriented Framework for the Development of AMS Circuit Generators

2014 PhD-Thesis BAG A Designer-Oriented Framework for the Development ...

2016 Book Transformer-BasedDesignTechniq

2016 Book Transformer-Based[..]

2017 Book OperationalAmplifiers

2017 Book OperationalAmplif[..]

2019 Book Digital Subsampling Phase Lock Techniques for Frequency Synthesis and Polar Transmission

2019 Book Digital Subsampling Phase Lock Techniques for Frequency ...

2019 Millimeter-Wave Circuits for 5G and Radar

2019 Millimeter-Wave Circuits for 5G and Radar

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled Buck Converter With A<sup>2</sup>-Comparator and Sleep-Time Detector for IoT Application

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled ...

Wenbin Huang & Lianxi Liu & Xufeng Liao & Chengzhi Xu & Yonyuan Li

24位96KSPSΣ-Δ调制器的设计

24位96KSPSΣ-Δ调制器的设计

A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI

A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI

25Gbps系统封装和高速互连的信号完整性的基础性研究

25Gbps系统封装和高速互连的信[..]

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR - Solid-State Circuits, IEEE Journal of

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...

393747_Print.indd

393747_Print.indd

3P-EBK: CALCULUS EARLY TRANSCENDENTALS

3P-EBK: CALCULUS EARLY TRANSCENDENTALS

A 470-nA Quiescent Current and 92.7%/94.7% Efficiency DCT/PWM Control Buck Converter With Seamless Mode Selection for IoT Application

A 470-nA Quiescent Current and 92.7%/94.7[..] Efficiency ...

5.0Gbps高速串行USB3.0数据发送器的设计

5.0Gbps高速串行USB3.0[..]

509764_1_En_Print.indd

509764_1_En_Print[..]

7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge (XAPP1286)

7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge ...

7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)

7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)

A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current Pre-Amplifier for High Frequency Lateral MEMS Oscillators

A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...

Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi

802.11 无线权威指南

802.11 无线权威指南

LAN/MAN Standards Committee of the IEEE Computer Society

AN 812: Platform Designer System Design Tutorial

AN 812: Platform Designer System Design Tutorial

Intel Corporation

93.张强-高性能Rail to Rail恒定跨导CMOS运算放大器

93.张强-高性能Rail to Rail恒定跨导CMOS运算放大器

<4D6963726F736F667420576F7264202D2046504741D6D0494FCAB1D0F2D4BCCAF8B7D6CEF62E646F63>

<4D6963726F736F66[..]

[Behzad Razavi] Phase-Locking in High-Performance (BookFi)

[Behzad Razavi] Phase-Locking in High-Performance (BookFi)

[集成电路掩膜板设计].IC.Mask.Design

[集成电路掩膜板设计].IC.Ma[..]

A TIA in CMOS 0.18um

A TIA in CMOS 0.18um

a-new-semiconductor-voltage-standard

a-new-semiconduct[..]

A0130105

A0130105

Abidi-Pan, Hui.University of California, Los Angeles

Abidi-Pan, Hui.University of California, Los Angeles

Abraham uta GPIO ESD

Abraham uta GPIO ESD

Accurate and Rapid Measurement of IP2 and IP3

Accurate and Rapid Measurement of IP2 and IP3