ADS2011射频电路设计与仿真实例
徐兴福著
ISSCC2021-SC4
未知
Session 11V-ADVANCED WIRELINE LINKS AND TECHNIQUES
Signal Processing for Wireless Communications (Boccuzzi, Joseph) ...
计算机图形学 几何体数据结构
Elmar Langetepe & Gabriel Zachmann
池保勇 CMOS射频集成电路分析与设计
控制系统设计指南 原书第4版
（美）乔治?埃利斯著
ISSCC2021-T1-Fund[..] of RF and Mm-Wave Power Amplifier Designs
二级运放建立时间与相位裕度的分析与优化
高等数学 第7版 上
同济大学数学系编
<CEA2BBFDB7D6D1A7[..]
lenovo
开关功率变换器——开关电源的原理、[..] (张懋 徐德鸿) (Z-Library)
作者
www.bzfxw.com
标准分享网
Microsoft Word - RDK FractN PLL Tutorial v1.0 090420
ramullen
一种高摆幅软启动线性稳压源设计
Microsoft Word - LNA.doc
Session 9
((stdin))
(thoma)
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(Analog Circuits and Signal Processing) Danica Stefanovic, Maher ...
Structu
(EE) Razavi, Design of Analog CMOS Integrated Circuits 2nd
-
0-306-47052-7_Boo[..]
A 0.46ps RJ<inf>rms</inf> 5GHz wideband LC PLL for multi-protocol ...
Chethan Rao & Alvin Wang & Shaishav Desai
A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process
Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin
0071509054.pdf
0132642786.pdf
Neil H. E. Weste
04_TechActive.fm
Administrator
A 1 GHz CMOS RF Front-End IC for a Direct-Conversion Wireless ...
IEEE
A 1.24 μA Quiescent Current NMOS Low Dropout Regulator With ...
Raveesh Magod & Bertan Bakkaloglu & Sanjeev Manandhar
A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier - Solid-State Circuits, ...
1.5Bit 级pipelined+ADC典型单[..]
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...
Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai
12bit pipeline ADC design
12位50Msps流水线A D转换器的研究与设计
14554110
14558797
14611382
14612565
14984226455248291[..]
14990665645773625[..]
16位高速CMOS流水线模数转换器[..] (1)
1V供电的低噪声带隙基准电压源
2-D Electromagnetic Simulation of Passive Microstrip Circuits
Alejandro D. Jimenez
A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State ...
2-Stage OTA Design
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
A 2.7-V 900-MHz CMOS LNA and Mixer - Solid-State Circuits, IEEE ...
2.7Gbps收发器中LVDS驱动[..]
2002 Book On-ChipESDProtect[..]
2004Beek
2005 Book ClockGeneratorsFo[..]
2010_FrontMatter_[..]
Steve Bonney
2014 PhD-Thesis BAG A Designer-Oriented Framework for the Development ...
2016 Book Transformer-Based[..]
2017 Book OperationalAmplif[..]
2019 Book Digital Subsampling Phase Lock Techniques for Frequency ...
2019 Millimeter-Wave Circuits for 5G and Radar
A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled ...
Wenbin Huang & Lianxi Liu & Xufeng Liao & Chengzhi Xu & Yonyuan Li
24位96KSPSΣ-Δ调制器的设计
CBJ
A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI
Author
25Gbps系统封装和高速互连的信[..]
A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...
310233_2_En_Print[..]
U6fonter
323326_Print.indd
0009172
393747_Print.indd
3P-EBK: CALCULUS EARLY TRANSCENDENTALS
417725_Print.indd
0002624
A 470-nA Quiescent Current and 92.7%/94.7[..] Efficiency ...
5.0Gbps高速串行USB3.0[..]
509764_1_En_Print[..]
0014813
7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge ...
Xilinx, Inc.
7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...
Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi
802.11 无线权威指南
LAN/MAN Standards Committee of the IEEE Computer Society