Session 9: ML Processors From Cloud to Edge
未知
现代控制理论 第2版 (张嗣瀛) (Z-Library)
Matching Analysis and the Design of Low Offset Amplifiers
相位噪声jitter基本定义
yzx
一种快速瞬态响应LDO的设计与实现
TOM
微波工程
David M. Pozar
DESIGN WITH OPERATIONAL AMPLIFIERS AND
CMOS高性能运算放大器研究与设计
模拟电子技术基础答案-第五版
12位50Msps流水线A D转换器的研究与设计
Front Matter
SHANTHI PAVAN, RICHARD SCHREIER & GABOR C. TEMES
Operation and Modeling of the MOS Transistor 3rd
低中频接收机中复数滤波器的设计
一种快速瞬态响应的无片外电容LDO的设计
ISSCC2021-SC4
A 470-nA Quiescent Current and 92.7%/94.7[..] Efficiency ...
一种快速瞬态响应双环路LDO稳压器的设计
eetop.cn TN07CLDR001 1 3
(Analog Circuits and Signal Processing) Danica Stefanovic, Maher ...
Structu
(EE) Razavi, Design of Analog CMOS Integrated Circuits 2nd
0-306-47052-7_Boo[..]
A 0.46ps RJ<inf>rms</inf> 5GHz wideband LC PLL for multi-protocol ...
Chethan Rao & Alvin Wang & Shaishav Desai
A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process
Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin
0071509054.pdf
0132642786.pdf
Neil H. E. Weste
04_TechActive.fm
Administrator
A 1 GHz CMOS RF Front-End IC for a Direct-Conversion Wireless ...
IEEE
A 1.24 μA Quiescent Current NMOS Low Dropout Regulator With ...
Raveesh Magod & Bertan Bakkaloglu & Sanjeev Manandhar
A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier - Solid-State Circuits, ...
1.5Bit 级pipelined+ADC典型单[..]
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...
Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai
12bit pipeline ADC design
14984226455248291[..]
14990665645773625[..]
16位高速CMOS流水线模数转换器[..] (1)
1V供电的低噪声带隙基准电压源
A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State ...
2-Stage OTA Design
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
A 2.7-V 900-MHz CMOS LNA and Mixer - Solid-State Circuits, IEEE ...
2.7Gbps收发器中LVDS驱动[..]
2002 Book On-ChipESDProtect[..]
2004Beek
2005 Book ClockGeneratorsFo[..]
2010_FrontMatter_[..]
Steve Bonney
2014 PhD-Thesis BAG A Designer-Oriented Framework for the Development ...
2016 Book Transformer-Based[..]
2017 Book OperationalAmplif[..]
2019 Book Digital Subsampling Phase Lock Techniques for Frequency ...
2019 Millimeter-Wave Circuits for 5G and Radar
A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled ...
Wenbin Huang & Lianxi Liu & Xufeng Liao & Chengzhi Xu & Yonyuan Li
24位96KSPSΣ-Δ调制器的设计
CBJ
A 25Gb/s PAM4 Transmitter in 90nm CMOS SOI
Author
25Gbps系统封装和高速互连的信[..]
A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...
393747_Print.indd
0009172
3P-EBK: CALCULUS EARLY TRANSCENDENTALS
5.0Gbps高速串行USB3.0[..]
509764_1_En_Print[..]
0014813
7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge ...
Xilinx, Inc.
7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
A 76 dB 1.7 GHz 0.18 m CMOS Tunable TIA Using Broadband Current ...
Hossein Miri Lavasani & Wanling Pan & Brandon Harrington & Reza Abdolvand & Farrokh Ayazi
802.11 无线权威指南
LAN/MAN Standards Committee of the IEEE Computer Society
AN 812: Platform Designer System Design Tutorial
Intel Corporation
93.张强-高性能Rail to Rail恒定跨导CMOS运算放大器
<4D6963726F736F66[..]
linjie
[Behzad Razavi] Phase-Locking in High-Performance (BookFi)
[集成电路掩膜板设计].IC.Ma[..]
A TIA in CMOS 0.18um
a-new-semiconduct[..]
A0130105
Preeti Sharma
Abidi-Pan, Hui.University of California, Los Angeles
Abraham uta GPIO ESD
Accurate and Rapid Measurement of IP2 and IP3
Ken Kundert