UNIX环境高级编程
W.RICHARD STEVENS
Session 8
未知
MIPI高速数据接口的研究与实现
[Behzad Razavi] Phase-Locking in High-Performance (BookFi)
Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: ...
IEEE
分类号 密级
USER
EDA与IC设计 CMOS集成电路后端设计与实战
刘峰编著
Totem User Manual 2021R
模拟CMOS集成电路设计 第2版14609998
Virtuoso Editing 的使用简介
Richey
Wiener-Khinchin theorem
Calibre® Local Printability Enhancement User's and Reference ...
Siemens Industry Software
模拟集成电路设计与仿真
何乐年
Microsoft PowerPoint - Bandgap and LDO.pptx
Administrator
RC OSCILLATOR WITH ADDITIONAL NVERTER IN SERIES WITH CAPACTOR
PLL Perfomance, Simulation, and Design
Dean Banerjee
Abraham uta GPIO ESD
天线（第三版）约翰克劳斯中文高清全本
Understanding Delta-Sigma Data Converters
Richard Schreier & GABOR C. TEMES
Understanding Delta-Sigma Data Converters 2nd edition
SHANTHI PAVAN, RICHARD SCHREIER & GABOR C. TEMES
Understanding Jitter and Phase Noise : A Circuits and Systems ...
Nicola Da Dalt; Ali Sheikholeslami & Ali Sheikholeslami
Understanding Jitter Requirements of PLL-Based Processors Application ...
ANALOG DEVICES INC.
Understanding Phase Noise in LC VCOs
A Key Problem in RF Integrated Circuits
Universal Serial Bus 3.0 Specification
Universal Verification Methodology (UVM) Cookbook
Functional Verification Methodology Team - Mentor & A Siemens Business
untitled
US6380806B1-Diffe[..] telescopic operational amplifier having ...
USB 2.0
hevryjiang
USB 3 1 r1.0
mphelps
USB 3.0中五分频电路设计
TOM
USB2.0协议中文版
Jungle
Using ADS to simulate Noise Figure using a large-signal transistor ...
Steve Long
Using the Python API to Develop Process Portable PyCells
Inc. Synopsys
UVM实战（卷Ⅰ)
张强编著
Verification of SD/MMC Controller IP Using UVM
Verilog HDL Design Examples
Joseph Cavanagh
verilog HDL那些事
akuei2
VerilogA系统设计与仿真（可[..]
Verilog数字VLSI设计教程
【作 者】李林编著
Verilog数字系统设计教程
Virtuoso Multi-Mode Simulation with Spectre Platform
Virtuoso Parameterized Cell Reference
Inc. Cadence Design Sys tems
Virtuoso Spectre Circuit Simulator RF Analysis Theory
Cadence Design Systems, Inc.
Virtuoso Visualization and Analysis XL User Guide
Vivado Design Suite User Guide: Logic Simulation (UG900)
Xilinx, Inc.
VLSI Physical Design: From Graph Partitioning to Timing Closure
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Voltus IC Power Integrity Solution User Guide
Voltus-Fi Hierarchical IR Drop and EM Analysis
Wideband RF PLL fractional/integer frequency synthesizer with ...
STMICROELECTRONICS
Wishbone B4
michael
WLAN射频接收机集成电路设计与研究
X-Parameters
DAVID E. ROOT
xCalibrate Batch User's Manual
Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,
Xilinx DS534, FIR Compiler v5.0, Data Sheet
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...
ZigBee低中频接收机中复数滤波[..]
《Linux从初学到精通》.(张勤[..]
《ModelSim电子系统分析及仿真》
《自动控制原理》[卢京潮 编著]
【汉化】Static Timing Analysis for Nanometer DesignsA Practical ...
一个全差分运放电路的设计
一款超低噪声快速启动的CMOS带隙[..] 刘鸿雁
一款轨到轨输入 输出运算放大器的设计与研究 辛国松
一种10 ppm oC低压CMOS带隙电压基准源设计 朱樟明
CNKI
一种LDO使能控制端失效的分析方法
一种低压CMOSLDO稳压电源电路
一种低噪声高电源抑制比CMOS低压[..]
一种低温漂CMOS带隙基准电压源的设计 陈碧
一种低静态电流、高稳定性的LDO线[..]
一种低静态电流瞬态增强的无电容型L[..]
一种具有温度补偿 高电源抑制比的带隙基准源 何捷
一种具有温度补偿 高电源抑制比的带隙基准源 何捷 (1)