Session 18
未知
THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...
iccad095
Tempus User Guide
Inc. Cadence Design Sys tems
Spectre Circuit Simulator Reference
一种基于LDO稳压器的带隙基准电压源设计
阻抗匹配与史密斯（Smith）圆图[..]
PrimeSim� HSPICE® User Guide: Basic Simulation and Analysis
Inc. Synopsys
FPGA数字信号处理设计教程-sy[..] generator入门与提高
自适应滤波器原理
（美）赫金 & 郑宝玉等译
verilog HDL那些事
akuei2
ISF_TUTORIAL
YIZHE HU
CN104391533A-High[..] (power supply rejection ratio) LDO (low ...
自动控制原理第6版
CMOS 射频集成电路分析与设计
一种应用于LDO的可编程电流限电路设计
Pages from M.E. Van Valkenburg - Network Analysis 6(1959, Prentice ...
libgen.lc-2
Session 9: ML Processors From Cloud to Edge
低压高速LDO电路系统的分析与设计
参考书 芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立
Analog Behavioral Modeling with the Verilog-A Language
Michiel Steyaert CMOS CELLULAR RECEIVER FRONT-ENDS
PoleZero.dvi
Dynamic Response of Linear Systems Impact of Pole & Zero Locations
ADI 技术指南合集
芯片I／O缓冲及ESD电路设计
eetop.cn Matching
ESD in Silicon Integrated Circuits
基于CMOS工艺的全芯片ESD保护[..]
esd-circuits-and-[..]
A mixed-mode esd protection circuit simulation-design methodology ...
CMOS电路芯片ESD保护电路设计[..] 赵近
ESD Design and Synthesis (1)
CN104601160B-灿芯半导[..]
DDR3存储器接口电路的设计与实现[..]
Design Procedures for Three-Stage CMOS OTAs With Nested-Miller ...
CMOS高性能运算放大器研究与设计
NoiseDesign.dvi
MOSAmpNoise.dvi
MIPI高速数据接口的研究与实现
Internal and external op-amp compensation: a control-centric ...
Distributed Loss-Compensation Techniques for Energy-Efficient ...
二级运放建立时间与相位裕度的分析与优化
一种适用于微传感器读出电路的低噪声[..]
Matching Analysis and the Design of Low Offset Amplifiers
Single miller capacitor frequency compensation technique for ...
te.2005.杨氏零点再发现
一种适用于微传感器读出电路的低噪声[..] (1)
93.张强-高性能Rail to Rail恒定跨导CMOS运算放大器
一款轨到轨输入 输出运算放大器的设计与研究 辛国松
Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input ...
US6380806B1-Diffe[..] telescopic operational amplifier having ...
反馈运算放大器电路的噪声分析和设计
工作在亚阈值区CMOS OTA的研究
tcsii.2005.A new modeling and optimization of gain-boosted cascode ...
ISM-PLL
DUTY CYCLE CORRECTION CIRCUITRY
DELAY LOCKLOOP CIRCUIT
14990665645773625[..]
基于 DLL倍频技术的 1GHz本地振荡器设计 英文 李金城
Frontmatter
2019 Book Digital Subsampling Phase Lock Techniques for Frequency ...
系统芯片中的全数字锁相环设计
thesis.dvi
锁相环型频率综合器中的高速分频器 袁泉
2004Beek
Wiener-Khinchin theorem
PLL频率合成器的杂散性能分析
14984226455248291[..]
锁相环相位噪声与环路带宽的关系分析
基于延迟锁相环的时钟发生器设计
全单片集成的多模CMOS正交频率综[..]
PHASE-INTERPOLATOR BASED PLL FREQUENCY SYNTHESIZER
PHASE ERROR CANCELLATION
PLL WITH LOW SPURS
MSSC.2016.B. Razavi-TSPC Logic
LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...
CN106357266B-华为20[..]
js.2010.PFD biased with shunt regulator