Generate ESD Source in ADS
TU,NASH (K-Taiwan,ex1)
Session 7: Imagers and Range Sensors
未知
Michiel Steyaert CMOS CELLULAR RECEIVER FRONT-ENDS
CN106656160A-上海集成[..]
Numerical Analysis
Richard L. Burden
一种10 ppm oC低压CMOS带隙电压基准源设计 朱樟明
CNKI
有限元方法(第五版)第一卷 基本原理
(英)O.C.Zienkiewicz (美)R.L.Taylor著
信号分析与处理_MATLAB语言及应用
http://www.pris.edu.cn
HFSS电磁仿真设计从入门到精通
IEEE Std 802.11g-2003 [Amendment to IEEE Std 802.11, 1999 Edition ...
LAN/MAN Standards Committee of the IEEE Computer Society
Analysis and Design of ESD Protection for Robust Low-Power Pierce ...
Kim B. Ostman & Erlend Strandvik & Phil Corbishley & Tor Oyvind Vedal & Mika Salmi
计算电磁学 by 王秉中,邵维 (z-lib.org)
verilog HDL那些事
akuei2
DELAY LOCKLOOP CIRCUIT
Numerical Analysis (Second Edition)
Walter Gautschi
一种低温漂CMOS带隙基准电压源的设计 陈碧
应用随机过程概率论模型导论 (Sheldon M.Ross) (Z-Library)
0-306-47052-7_Boo[..]
芯片I/O缓冲及ESD电路设计
eetop.cn Matching
ESD in Silicon Integrated Circuits
基于CMOS工艺的全芯片ESD保护[..]
esd-circuits-and-[..]
A mixed-mode esd protection circuit simulation-design methodology ...
CMOS电路芯片ESD保护电路设计[..] 赵近
ESD Design and Synthesis (1)
CN104601160B-灿芯半导[..]
DDR3存储器接口电路的设计与实现[..]
Design Procedures for Three-Stage CMOS OTAs With Nested-Miller ...
CMOS高性能运算放大器研究与设计
NoiseDesign.dvi
MOSAmpNoise.dvi
MIPI高速数据接口的研究与实现
Internal and external op-amp compensation: a control-centric ...
Distributed Loss-Compensation Techniques for Energy-Efficient ...
二级运放建立时间与相位裕度的分析与优化
一种适用于微传感器读出电路的低噪声[..]
Matching Analysis and the Design of Low Offset Amplifiers
Single miller capacitor frequency compensation technique for ...
te.2005.杨氏零点再发现
一种适用于微传感器读出电路的低噪声[..] (1)
93.张强-高性能Rail to Rail恒定跨导CMOS运算放大器
一款轨到轨输入 输出运算放大器的设计与研究 辛国松
Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input ...
US6380806B1-Diffe[..] telescopic operational amplifier having ...
反馈运算放大器电路的噪声分析和设计
工作在亚阈值区CMOS OTA的研究
tcsii.2005.A new modeling and optimization of gain-boosted cascode ...
ISM-PLL
DUTY CYCLE CORRECTION CIRCUITRY
14990665645773625[..]
基于 DLL倍频技术的 1GHz本地振荡器设计 英文 李金城
Frontmatter
2019 Book Digital Subsampling Phase Lock Techniques for Frequency ...
系统芯片中的全数字锁相环设计
thesis.dvi
锁相环型频率综合器中的高速分频器 袁泉
2004Beek
Wiener-Khinchin theorem
PLL频率合成器的杂散性能分析
14984226455248291[..]
锁相环相位噪声与环路带宽的关系分析
基于延迟锁相环的时钟发生器设计
全单片集成的多模CMOS正交频率综[..]
PHASE-INTERPOLATOR BASED PLL FREQUENCY SYNTHESIZER
PHASE ERROR CANCELLATION
PLL WITH LOW SPURS
MSSC.2016.B. Razavi-TSPC Logic
LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...
CN106357266B-华为20[..]
js.2010.PFD biased with shunt regulator
CN103036558B-SMIC[..]
ISSCC2021-SC4
ISSCC2021-SC2
ISSCC2021-SC1
ISSCC2021-SC3
CN105763219A-2016[..]