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Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...

Shih-An Yu & Peter R. Kinget

离散时间控制系统（第二版） Katsuhiko ； Ogata (z-lib.org)

离散时间控制系统（第二版） Katsuhiko ； Ogata (z-lib.org)

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...

Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin

Design techniques for cascoded CMOS op amps with improved PSRR and common-mode input range

Design techniques for cascoded CMOS op amps with improved PSRR ...

D.B. Ribner & M.A. Copeland

LDO过流与温度保护电路的分析与设计

LDO过流与温度保护电路的分析与设计

Session 3: Highlighted Chip Releases: Modern Digital SoCs

Session 3: Highlighted Chip Releases: Modern Digital SoCs

学校代码： 10246

学校代码： 10246

基于延迟锁相环的时钟发生器设计

基于延迟锁相环的时钟发生器设计

Microsoft Word - 0TitlePageVbook.doc

Microsoft Word - 0TitlePageVbook.doc

锁相环(PLL)电路设计与应用

锁相环(PLL)电路设计与应用

(日)远坂俊昭著何希才译

电子电路的计算机辅助分析与设计方法.汪蕙

电子电路的计算机辅助分析与设计方法.汪蕙

Session 22

Session 22

HIGH QUALITY PARALLEL RESONANCE OSCILLATOR

HIGH QUALITY PARALLEL RESONANCE OSCILLATOR

A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State Circuits, IEEE Journal of

A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State ...

CMOS模拟集成电路设计

CMOS模拟集成电路设计

（美）艾伦，（美）霍尔伯格著

Dynamic Analysis of Switching-Mode DC DC Converters-Springer Netherlands (1991)

Dynamic Analysis of Switching-Mode DC DC Converters-Springer ...

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...

Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly

Kendall Su, Analog Filters, 2nd Ed.

Kendall Su, Analog Filters, 2nd Ed.

Books

低电压CMOS分数分频锁相环频率综合器关键技术研究

低电压CMOS分数分频锁相环频率综合器关键技术研究

全单片集成的多模CMOS正交频率综合器的研究

全单片集成的多模CMOS正交频率综[..]

PHASE-INTERPOLATOR BASED PLL FREQUENCY SYNTHESIZER

PHASE-INTERPOLATOR BASED PLL FREQUENCY SYNTHESIZER

$Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs$

Wideband RF PLL fractional/integer frequency synthesizer with ...

STMICROELECTRONICS

PHASE ERROR CANCELLATION

PHASE ERROR CANCELLATION

PLL WITH LOW SPURS

PLL WITH LOW SPURS

MSSC.2016.B. Razavi-TSPC Logic

MSSC.2016.B. Razavi-TSPC Logic

Noise and Spurious Tones Management Techniques for Multi-GHz RF-CMOS Frequency Synthesizers Operating in Large Mixed Analog-Digital SOCs

Noise and Spurious Tones Management Techniques for Multi-GHz ...

LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References Cited DETECTING METHOD

LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...

CN106357266B-华为2016-锁定检测电路、方法及锁相电路-带offset电流

CN106357266B-华为20[..]

硅基压控振荡器的研究与设计电子科技大学彭羽

硅基压控振荡器的研究与设计电子科技大学彭羽

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm CMOS

A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...

Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly

js.2010.PFD biased with shunt regulator

js.2010.PFD biased with shunt regulator

The Problem of PLL Power Consumption

The Problem of PLL Power Consumption

基于自偏置技术的锁相环设计刘克赛2019

基于自偏置技术的锁相环设计刘克赛2019

CN103036558B-SMIC2015-扩展线性范围的v2i

CN103036558B-SMIC[..]

ISSCC2021-SC4

ISSCC2021-SC4

ISSCC2021-SC2

ISSCC2021-SC2

ISSCC2021-SC1

ISSCC2021-SC1

ISSCC2021-SC3

ISSCC2021-SC3

CN105763219A-2016-一种占空比为25%的分频器

CN105763219A-2016[..]

Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...

Shih-An Yu & Peter R. Kinget

Smoothing the Way for Digital Phase-Locked Loops: Clock Generation in the Future with Digital Signal Processing for Mitigating Spur and Interference

Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...

Cheng-Ru Ho & Mike Shuo-Wei Chen

一种自参考结构的高速高精度片上时钟抖动测量系统

一种自参考结构的高速高精度片上时钟[..]

USB 3.0中五分频电路设计

USB 3.0中五分频电路设计

模拟集成电路信号完整性中抖动与振铃问题的研究

模拟集成电路信号完整性中抖动与振铃[..]

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS SerDes FPGAs

Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...

Rakesh H. Patel & William Bereza

适合通信应用的低功耗55纳米12 省略 0 MSps双通道流水线型ADC 陈宏铭

适合通信应用的低功耗55纳米12 省略 0 MSps双通道流水线型ADC 陈宏铭

基于功耗优化的Pipelined+ADC系统结构设计与关键单元研究 (1)

基于功耗优化的Pipelined+[..] (1)

16位高速CMOS流水线模数转换器关键技术研究 (1)

16位高速CMOS流水线模数转换器[..] (1)

Sampled Systems and the Effects of Clock Phase Noise and Jitter Application Note (AN-756)

Sampled Systems and the Effects of Clock Phase Noise and Jitter ...

Analog Devices, Inc.

AD9635 cn

AD9635 cn

12位50Msps流水线A D转换器的研究与设计

12位50Msps流水线A D转换器的研究与设计

Aperture Uncertainty and ADC System Performance Application Note (AN-501)

Aperture Uncertainty and ADC System Performance Application ...

Analog Devices, Inc.

MT-001: Taking the Mystery out of the Infamous Formula,'SNR = 6.02N + 1.76dB,' and Why You Should Care

MT-001: Taking the Mystery out of the Infamous Formula,'SNR ...

1.5Bit 级pipelined+ADC典型单级电路结构实现研究

1.5Bit 级pipelined+ADC典型单[..]

比较器失调的仿真方法

比较器失调的仿真方法

高速模数转换器动态参数的定义和测试

高速模数转换器动态参数的定义和测试

适宜于系统集成的高速高精度模数转换电路设计技术研究-李福乐

适宜于系统集成的高速高精度模数转换[..]

应用于流水线ADC的比较器的设计与研究

应用于流水线ADC的比较器的设计与研究

12bit pipeline ADC design

12bit pipeline ADC design

高性能流水线模数转换器及其数字校准技术研究贾华宇

高性能流水线模数转换器及其数字校准[..] 贾华宇

CMOS Sigma-Delta Converters Practical Design Guide

CMOS Sigma-Delta Converters Practical Design Guide

通信标准对数据转换器的要求V1.0

通信标准对数据转换器的要求V1.0

RF Sampling for Multi-band Radios

RF Sampling for Multi-band Radios

Texas Instruments, Incorporated [SBAA328,*]

SAR A／D转换器中电容失配问题的分析

SAR A／D转换器中电容失配问题的分析

SAR ADC-MIT

SAR ADC-MIT

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching Procedure

A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...

Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li

Abidi-Pan, Hui.University of California, Los Angeles

Abidi-Pan, Hui.University of California, Los Angeles

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with over 80-dB SFDR - Solid-State Circuits, IEEE Journal of

A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...

e采样与adc

e采样与adc

Advanced data converters G Manganaro

Advanced data converters G Manganaro

HIGH SPEED AND LOW POWER DYNAMIC LATCH COMPARATOR

HIGH SPEED AND LOW POWER DYNAMIC LATCH COMPARATOR

低压、低功耗、高精度的逐次逼近型

低压、低功耗、高精度的逐次逼近型

Continuous-Time Sigma-Delta AD Conversion Fundamentals, Performance Limits and Robust Implementations by Friedel Gerfers, Maurits Ortmanns (z-lib.org)

Continuous-Time Sigma-Delta AD Conversion Fundamentals, Performance ...

TrnoiseAN.fm

TrnoiseAN.fm

mssc.2015.Razavi-The StrongARM Latch

mssc.2015.Razavi-The StrongARM Latch

高速低功耗SAR ADC的关键技术研究与系统设计

高速低功耗SAR ADC的关键技术研究与系统设计