模拟CMOS电路设计折中与优化
未知
A precise on-chip voltage generator for a gigascale dram with ...
IEEE
Precise delay generation using coupled oscillators
J.G. Maneatis & M.A. Horowitz
2014 PhD-Thesis BAG A Designer-Oriented Framework for the Development ...
一种LDO使能控制端失效的分析方法
现代控制理论 第2版 (张嗣瀛) (Z-Library)
一种带过温保护和折返电流限的LDO设计
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zeng zhen
DCDC-EECS-2011-94
一种应用于LDO的可编程电流限电路设计
最优控制理论与应用
ADI 技术指南合集
Using the Python API to Develop Process Portable PyCells
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CMOS低压差线性稳压器 [王忆，何乐年 著] 2012年
Totem User Manual 2021R
3P-EBK: CALCULUS EARLY TRANSCENDENTALS
控制之美（卷1）——控制理论从传递[..]
王天威
TMTT 202212
StarRC User Guide and Command Reference
Synopsys, Inc.
TCASⅡ 202212
JSSC 202212
控制之美 卷1 (王天威) (Z-Library)
High-Speed System and Analog InputOutput Design Thanh T. Tran
PlanarSpiralInduc[..]
Layout Techniques for Integrated Circuit Designers
Sahrling
The Method of Moments in Electromagnetics
Walton C. Gibson
模拟集成电路分析与设计 洪志良
FinFET Devices for VLSI Circuits and Systems
Samar K. Saha
High Efficiency RF and Microwave Solid State Power Amplifiers
Paolo Colantonio, Franco Giannini & Ernesto Limiti
Solution-for-Design of Analog CMOS Integrated Circuits 2nd
509764_1_En_Print[..]
0014813
RF Microelectronics 2nd
Modelithics Optimized LNA Design April MWJ 2021
Artificial Intelligence: A Modern Approach, Global Edition, ...
Stuart Russell / Peter Norvig
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模拟CMOS集成电路 第二版 拉扎维 by 拉扎维 (z-lib.org)
Sahrling M. Analog Circuit Simulators for Integrated Circuit ...
Fundamentals of High Frequency CMOS Analog Integrated Circuits, ...
Digitally-assisted design of data converters
4<8=8AB@0B>@
The advanced part of A treatise on the dynamics of a system ...
Routh, Edward John, 1831-1907.
Pages from M.E. Van Valkenburg - Network Analysis 6(1959, Prentice ...
libgen.lc-2
Practical RF Amplifier Design and Performance Optimization with ...
在线作Bode/Nyquis
yzx
《自动控制原理》[卢京潮 编著]
The Problem of PLL Power Consumption
Behzad Razavi
Presentation
Gaurav Singh
Microsoft PowerPoint - plenary_2021_reserve
Albert
Session 3
ISSCC2021-T8-On-Chip Interconnects Basic Concepts, Designs, ...
ISSCC2021-T6-Basics of DAC-based Wireline Transmitters
ISSCC2021-SC4
ISSCC2021-SC4-Pro[..] Clock Generation, Distribution, and Clock ...
ISSCC2021-SC3-Clo[..] Clock Distribution, and Clock Management ...
ISSCC2021-SC3
ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application ...
ISSCC2021-SC2
ISSCC2021-SC1-Int[..] to PLLs Phase Noise, Modeling, and Key ...
ISSCC2021-SC1
ISSCC2021-T11-Ult[..] Power Wireless Receiver Design
ISSCC2021-T10-Fun[..] of Fully-Integrated Voltage Regulators
ISSCC2021-T9-Desi[..] Amplifiers for Stability
ISSCC2021-T7-Basic Design Approaches to Accelerating Deep Neural ...
ISSCC2021-T5-Cali[..] Techniques in ADCs
ISSCC2021-T4-Meas[..] and Evaluating the Security Level of ...
ISSCC2021-T3-Silicon Photonics – from Basics to ASICs
ISSCC2021-T1-Fund[..] of RF and Mm-Wave Power Amplifier Designs
ISSCC2021-T2-Fund[..] of Memory Subsystem Design for HPC and ...
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Session 32
Session 31
Session 30