Session 29V
未知
FPGA数字信号处理设计教程：Sy[..] Generator入门与提高 11938681
一种具有温度补偿 高电源抑制比的带隙基准源 何捷 (1)
LDO工作原理详解
射频集成电路与系统
李智群 王志功 编著
PrimeSim� CCK Reference Manual
Inc. Synopsys
Microwave Circuit Design: A Practical Approach Using ADS
Yeom, Kyung-Whan
半导体物理学 （第七版）
1V供电的低噪声带隙基准电压源
Fundamentals of Digital Logic with Verilog Design, THIRD EDITION
Stephen Brown & Zvonko Vranesic
X-Parameters
DAVID E. ROOT
Abidi-Pan, Hui.University of California, Los Angeles
7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge ...
Xilinx, Inc.
一种快速瞬态响应双环路LDO稳压器的设计
Session 20
TheDesigner’sGuid[..]
低压低功耗CMOS带隙电压基准及启[..] 许长喜
硅基压控振荡器的研究与设计 电子科技大学 彭羽
China
简并点优化的高性能带隙基准电路 应建华
基于MOSFET失配分析的低压高精[..] 刘帘曦
Microsoft PowerPoint - 第十一章 带隙基准 [兼容模式]
低压低功耗电流模CMOS带隙基准电路 孔令荣
TEMPERATURE AND PROCESS (56) COMPENSATED CURRENT REFERENCE CIRCUITS
LDO LINEAR REGULATOR WITH IMPROVED TRANSIENT RESPONSE
AMPLIFIER ARCHITECTURE AND APPLICATION THEREOF TO A BAND-GAP ...
A detailed analysis of power-supply noise attenuation in bandgap ...
A precise on-chip voltage generator for a gigascale dram with ...
IEEE
sido buck converter
Duyu Liu & Xinzhi Liu & Hao Chen & Shouming Zhong
Research and Design of Buck-Boost DC-DC Converter
CNKI
eetop.cn (Paper)The Flipped Voltage Follower A Useful Cell for
Analysis and design of monolithic, high PSR, linear regulators ...
compact trimming design of a high precision reference
A 1.24 μA Quiescent Current NMOS Low Dropout Regulator With ...
Raveesh Magod & Bertan Bakkaloglu & Sanjeev Manandhar
一种具有温度补偿 高电源抑制比的带隙基准源 何捷
一种高性能CMOS带隙电压基准源设计 朱樟明
简并点优化的高性能带隙基准电路
工作于亚阈值区的偏置基准电路-峰值电流镜
高精度带隙基准电压源的研究与设计
iData
电源芯片中CMOS带隙基准源与微调[..] (1)
Low-Cost Low-Power 2.4 GHz RF Transceiver datasheet (Rev. C)
Texas Instruments, Incorporated [SWRS040,C
Nested Miller compensation in low-power CMOS design
Ka Nang Leung;P.K.T. Mok
RC OSCILLATOR WITH ADDITIONAL NVERTER IN SERIES WITH CAPACTOR
高精度sigma-delta ADC设计研究与实现
一种具有采样保持功能的开关电容积分器 宋文清
基于Latch的CMOS动态比较器的研究
低压、低功耗、高精度的逐次逼近型
ycp
Advanced data converters G Manganaro
e采样与adc
A 3.3-V 12-b 50-MS/s A/D converter in 0.6-/spl mu/m CMOS with ...
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...
Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin
SAR A／D转换器中电容失配问题的分析
RF Sampling for Multi-band Radios
Texas Instruments, Incorporated [SBAA328,*]
CMOS Sigma-Delta Converters Practical Design Guide
4<8=8AB@0B>@
高性能流水线模数转换器及其数字校准[..] 贾华宇
12bit pipeline ADC design
应用于流水线ADC的比较器的设计与研究
高速模数转换器动态参数的定义和测试
比较器失调的仿真方法
jason
1.5Bit 级pipelined+ADC典型单[..]
12位50Msps流水线A D转换器的研究与设计
Sampled Systems and the Effects of Clock Phase Noise and Jitter ...
Analog Devices, Inc.
16位高速CMOS流水线模数转换器[..] (1)
基于功耗优化的Pipelined+[..] (1)
适合通信应用的低功耗55纳米12 省略 0 MSps双通道流水线型ADC 陈宏铭
Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...
Rakesh H. Patel & William Bereza
参考书 芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立
模拟集成电路信号完整性中抖动与振铃[..]
USB 3.0中五分频电路设计
TOM
Smoothing the Way for Digital Phase-Locked Loops: Clock Generation ...
Cheng-Ru Ho & Mike Shuo-Wei Chen
Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...
Shih-An Yu & Peter R. Kinget
CN105763219A-2016[..]
基于自偏置技术的锁相环设计 刘克赛2019
刘克赛
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...
Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly
LOCK DETECTION CIRCUIT AND LOCK (56) Oct. 18, 2011 References ...
Noise and Spurious Tones Management Techniques for Multi-GHz ...
Adrian Maxim
THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...
iccad095