Session 33
未知
Microsoft Word - PREAMBLE.DOC
Administrator
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
带使能端及保护电路的LDO设计
<4D6963726F736F66[..]
linjie
Session 35: Adaptive Digital Techniques for Variation Tolerant ...
EESM692
Prof. Alex Leung
模拟IC设计
格雷
Cadence高速电路板设计
模拟IC 艾伦课件
SystemVerilog 验证方法学 - Verification Methodology Manual for SystemVerilog
Janick Bergeron & Eduard Cemy & Alan Hunter & Andrew Nightingale 著 & 夏宇闻 译
Session 32: Frequency Synthesizers
Low-noise monolithic amplifier design: Bipolar versus CMOS
运算放大器 理论与设计 9影印版 （荷）惠意欣著
适宜于系统集成的高速高精度模数转换[..]
深亚微米FPGA结构与CAD设计 12083165 2
PHASE ERROR CANCELLATION
Microsoft PowerPoint - lect.08.RFSimulation [호환 모드]
jaeha
MIMO-OFDM无线通信技术及M[..] WIRELESS COMMUNICATIONS WITH MATLAB
（韩）YONG SOO CHO，JAEKWON KIM，WON YONG YANG，CHUNG G.KANG著；孙锴，黄威译