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Numerical Methods for Ordinary Differential Equations by J. C. Butcher (z-lib.org)

Numerical Methods for Ordinary Differential Equations by J. ...

jssc.2005.Replica Compensated Linear Regulators for PLLs

jssc.2005.Replica Compensated Linear Regulators for PLLs

python 数值分析

python 数值分析

Mirella Misiaszek

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN PHY

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...

模拟集成电路设计与仿真-何乐年

模拟集成电路设计与仿真-何乐年

低功耗的高速高精度运放设计

低功耗的高速高精度运放设计

阻抗匹配与史密斯（Smith）圆图：基本原理

阻抗匹配与史密斯（Smith）圆图[..]

普林斯顿微积分读本（修订版）

普林斯顿微积分读本（修订版）

天线（第三版）约翰克劳斯中文高清全本

天线（第三版）约翰克劳斯中文高清全本

Continuous-Time Delta-Sigma Modulators for High-Speed AD Conversion Theory, Practice and Fundamental Performance Limits by James A. Cherry, W. Martin Snelgrove (auth.) (z-lib.org)

Continuous-Time Delta-Sigma Modulators for High-Speed AD Conversion ...

PLL WITH LOW SPURS

PLL WITH LOW SPURS

PowerManagmentIC

PowerManagmentIC

SPI Block Guide V4

SPI Block Guide V4

Freescale Semiconductor, Inc.

Computer Arithmetic - Algorithms and Hardware Designs

Computer Arithmetic - Algorithms and Hardware Designs

Virtuoso Parameterized Cell Reference

Virtuoso Parameterized Cell Reference

Inc. Cadence Design Sys tems

ADS射频电路设计与仿真从入门到精通

ADS射频电路设计与仿真从入门到精通

Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level

Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture ...

Digital integrated circuit design using verilog and systemverilog (Ronald Mehler) (z-lib.org)

Digital integrated circuit design using verilog and systemverilog ...

Category: VHDL

Avalon Verification IP Suite User Guide

Avalon Verification IP Suite User Guide

Altera Corporation