js.2010.PFD biased with shunt regulator
未知
数值分析
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin
Advanced Analog Building Blocks
Shen
Chap1_20160228_4.dvi
高速低功耗逐次逼近型模数转换器的研[..]
Vivado Design Suite User Guide: Logic Simulation (UG900)
Xilinx, Inc.
Voltus-Fi Hierarchical IR Drop and EM Analysis
现代控制系统 第12版
(美)RECHARD C.DORF,ROBERT H.BISHOP著;谢红卫,孙志强,宫二玲,经纪阳译
A 10-bit 50-MS/s SAR ADC With a Monotonic Capacitor Switching ...
Chun-Cheng Liu;Soon-Jyh Chang;Guan-Ying Huang;Ying-Zu Lin
基于0.13μm SOI CMOS工艺的高性能LDO设计
集成电路掩模设计-基础版图技术
基于ac620的fpga系统设计与[..]
Administrator
CMOS 射频集成电路分析与设计
Cadence Physical Verifi cation User Guide
Inc. Cadence Design Sys tems
深亚微米FPGA结构与CAD设计 12083165 2
深亚微米CMOS工艺ESD器件结构[..]
微软用户
Quantus Techgen Reference Manual
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-MM Interface ...
Intel Corporation