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IEEE Standard for Information Technology—Telecommunications and information exchange between systems—LANs and MANs—Specific requirements—Part 11: WLAN MAC and PHY Specifications—Amendment 5: Enhancements for Higher Throughput

IEEE Standard for Information Technology—Teleco[..] and information ...

LAN/MAN Standards Committee of the IEEE Computer Society

Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...

Shih-An Yu & Peter R. Kinget

Analysis and Design of Monolithic, High PSR, Linear Regulators for SoC Applications

Analysis and Design of Monolithic, High PSR, Linear Regulators ...

王华老师射频功放教材

王华老师射频功放教材

CMOS低压差线性稳压器 [王忆，何乐年著] 2012年

CMOS低压差线性稳压器 [王忆，何乐年著] 2012年

数字VLSI芯片设计使用Cadence和Synopsys CAD工具

数字VLSI芯片设计使用Cadence和Synopsys CAD工具

艾瑞克·布鲁范德著

EDA与IC设计 CMOS集成电路后端设计与实战

EDA与IC设计 CMOS集成电路后端设计与实战

High Speed Data Converters

High Speed Data Converters

Analysis and design of monolithic, high PSR, linear regulators for SoC applications - SOC Conference, 2004. Proceedings. IEEE International

Analysis and design of monolithic, high PSR, linear regulators ...

MCU芯片的复位电路与多模式时钟系统设计

MCU芯片的复位电路与多模式时钟系统设计

Advanced Analog Building Blocks

Advanced Analog Building Blocks

CMOS集成电路版图+概念、方法与工具（带书签）

CMOS集成电路版图+概念、方法与[..]

Tempus User Guide

Tempus User Guide

Inc. Cadence Design Sys tems

Signal and Power Integrity - Simplified, Third edition

Signal and Power Integrity - Simplified, Third edition

USB 3 1 r1.0

USB 3 1 r1.0

高等数学第7版上

高等数学第7版上

同济大学数学系编

Digital Integrated Circuits Analysis and Design

Digital Integrated Circuits Analysis and Design

高速数字电路设计中信号完整性分析与研究

高速数字电路设计中信号完整性分析与研究

Category: End Point

Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-MM Interface for PCI Express* User Guide

Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-MM Interface ...

Intel Corporation