理工书库 lilin | Category: Programming Model

Discover (Random Books)

Session 22

Session 22

CMOS集成电路中静电防护电路的设计与研究

CMOS集成电路中静电防护电路的设[..]

2-Stage OTA Design

2-Stage OTA Design

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN PHY

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...

Microsoft Word - RFKitDoc_v1 3.doc

Microsoft Word - RFKitDoc_v1 3.doc

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process

Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li

SAR A／D转换器中电容失配问题的分析

SAR A／D转换器中电容失配问题的分析

阻抗匹配与史密斯（Smith）圆图：基本原理

阻抗匹配与史密斯（Smith）圆图[..]

Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits Advances in Analog Circu

Next-Generation ADCs, High-Performance Power Management, and ...

《自动控制原理》[卢京潮编著]

《自动控制原理》[卢京潮编著]

12位50Msps流水线A D转换器的研究与设计

12位50Msps流水线A D转换器的研究与设计

PHASE-INTERPOLATOR BASED PLL FREQUENCY SYNTHESIZER

PHASE-INTERPOLATOR BASED PLL FREQUENCY SYNTHESIZER

Seven Steps to Successful Analog-to-Digital Signal Conversion (Noise Calculation for Proper Signal Conditioning) (Rev. 0)

Seven Steps to Successful Analog-to-Digital Signal Conversion ...

Analog Devices, Inc.

Continuous-Time Delta-Sigma Modulators for High-Speed AD Conversion Theory, Practice and Fundamental Performance Limits by James A. Cherry, W. Martin Snelgrove (auth.) (z-lib.org)

Continuous-Time Delta-Sigma Modulators for High-Speed AD Conversion ...

Digital Control

Digital Control

概率论与数理统计 (同济大学数学系) (Z-Library)

概率论与数理统计 (同济大学数学系) (Z-Library)

2005 Book ClockGeneratorsForSOCProcessor

2005 Book ClockGeneratorsFo[..]

ISSCC2021-SC3-Clocking, Clock Distribution, and Clock Management in WirelineWireless Subsystems

ISSCC2021-SC3-Clo[..] Clock Distribution, and Clock Management ...

Category: Programming Model

Nios II Processor Reference Guide

Nios II Processor Reference Guide

Intel Corporation