理工书库 lilin | Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

Discover (Random Books)

Analog Circuit Design Volume Three

Analog Circuit Design Volume Three

Bob Dobkin,John Hamburger

2002 Book On-ChipESDProtectionForIntegra

2002 Book On-ChipESDProtect[..]

数字设计原理与实践第4版影印版英文版=DIGITAL DESIGN PRINCIPLES AND PRACTIEES FOURTH EDITION

数字设计原理与实践第4版影印版英文版=DIGITAL DESIGN PRINCIPLES AND PRACTIEES ...

（美）韦克利（JOHN F.WAKERLY）著

一种低压CMOSLDO稳压电源电路

一种低压CMOSLDO稳压电源电路

USB2.0协议中文版

USB2.0协议中文版

0-306-47052-7_BookFrontmatter_OnlinePDF.pdf

0-306-47052-7_Boo[..]

Kluwer - The Designer's Guide to Spice and Spectre.tif

Kluwer - The Designer's Guide to Spice and Spectre.tif

FinFET Devices for VLSI Circuits and Systems

FinFET Devices for VLSI Circuits and Systems

基于自偏置技术的锁相环设计刘克赛2019

基于自偏置技术的锁相环设计刘克赛2019

SSReader Print.

SSReader Print.

微电子电路第5版（下册） (Adel S. Sedra, Kenneth C. Smith etc.) (Z-Library)

微电子电路第5版（下册） (Adel S. Sedra, Kenneth C. Smith etc.) (Z-Library)

半导体物理与器件（第三版）

半导体物理与器件（第三版）

(Analog Circuits and Signal Processing) Danica Stefanovic, Maher Kayal

(Analog Circuits and Signal Processing) Danica Stefanovic, Maher ...

PCI Express Base r3.0

PCI Express Base r3.0

一种适用于DDR内存驱动的LDO芯片设计

一种适用于DDR内存驱动的LDO芯片设计

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN PHY

THE DESIGN OF MASTER-SLAVE DLL FOR DDR2 SDRAM CONTROLLER IN ...

数字集成电路物理设计

数字集成电路物理设计

陈春章艾霞王国雄编著

Elementary Differential Equations and Boundary Value Problems

Elementary Differential Equations and Boundary Value Problems

William E. Boyce & Richard C. Diprima & Douglas B. Meade

Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)