数值分析
未知
Modeling Jitter in PLL-based Frequency Synthesizers
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jrproc.1950.Bothw[..] F.E.-Nyquist Diagrams and the Routh-Hurwitz ...
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学校代码： 10246
tcheng
Assura Physical Verifica tion User Guide
Inc. Cadence Design Sys tems
Static timing analysis for nanometer designs a practical approach ...
Scaling LC Oscillators in Nanometer CMOS Technologies to a Smaller ...
Shih-An Yu & Peter R. Kinget
华侨大学模拟IC实验8 无缓冲两级运放设计
USER
CN101969305B-威盛电子[..] conversion circuit
Analog-to-Digital Conversion
Operational Transconductance Amplifiers “OTAs”
Bernhard Boser
一种基于LDO稳压器的带隙基准电压源设计
深亚微米CMOS工艺ESD器件结构[..]
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Digital Integrated Circuits Analysis and Design
John E. Ayers
Session 25
Session 8: Ultra-High-Speed Wireline
HIGH QUALITY PARALLEL RESONANCE OSCILLATOR
IEEE Standard for Ethernet
Triple-Speed Ethernet Intel® FPGA IP User Guide
Intel Corporation