finite elemennt anlysis in ansys
kubik
计算电磁场的矩量法（PDF）
未知
Modeling Jitter in PLL-based Frequency Synthesizers
Ken Kundert
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin
模拟IC设计
格雷
Design of Low Noise Amplifiers
Steve Long
Microsoft Word - AXI protocol 翻译.doc
<C0EECBB6>
电路
丘关源
US6380806B1-Diffe[..] telescopic operational amplifier having ...
A 0.46ps RJ<inf>rms</inf> 5GHz wideband LC PLL for multi-protocol ...
Chethan Rao & Shaishav Desai & Alvin Wang
Robust Design of LV/LP Low-Distortion CMOS Rail-to-Rail Input ...
DesignWare Foundation Cores Installation and Setup Guide, Version ...
Synopsys, Inc.
IEEE Std 802.11ac™-2013, IEEE Standard for Information technology—Teleco[..] ...
LAN/MAN Standards Committee of the IEEE Computer Society
Electromagnetics for High-speed Analog and Digital Communication ...
Ali M. Niknejad
带隙基准电路的研究
<CCC6B3A4CEC4>
Analog Behavioral Modeling with the Verilog-A Language
Design Optimization of Power and Area of Two-Stage CMOS Operational ...
Telugu Maddileti;Govindarajulu Salendra;Chandra Mohan Reddy ...
LDO中过温保护电路的设计
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Xilinx, Inc.