Session 17: DC-DC Converters
未知
Avalon® Interface Specifications
Intel Corporation
Verilog HDL Design Examples
Joseph Cavanagh
PrimeWave� Design Environment for Reliability Analysis User ...
Inc. Synopsys
jssc.2005.Replica Compensated Linear Regulators for PLLs
CMOS模拟集成电路设计与仿真实例[..] ADE
Session 14: mm-Wave Transceivers for Communication and Radar
Perl实例精解(原书第4版)
A 0.46ps RJ<inf>rms</inf> 5GHz wideband LC PLL for multi-protocol ...
Chethan Rao & Shaishav Desai & Alvin Wang
Harmonic balance finite element method applications in nonlinear ...
Herbst-MIT2011--A Low-Noise Bandgap Voltage Reference Employing ...
Noise in Solid-state Devices and Lasers
A compact power-efficient 3 V CMOS rail-to-rail input/output ...
IEEE
Session 10: Continuous-Time ADCs and DACs
低压低功耗Sigma Delta调制器综述 吕立山
CNKI
一种低温漂CMOS带隙基准电压源的设计 陈碧
锁相环技术(第3版)——Phase[..] Techniques, Third Edition
Floyd M. Gardner 著 & 姚剑清 & 译
Session 35
Vivado Design Suite User Guide: Logic Simulation (UG900)
Xilinx, Inc.