A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...
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Operational Amplifiers Theory and Design (Johan Huijsing (auth.)) ...
未知
最优控制理论与应用
Sigma-Delta Converters. Practical Design Guide (José M. de la ...
模拟集成电路设计精粹——Analog Design Essentials
Willy M.C. Sansen 著 & 陈莹梅 译 & 王志功 审校
Using ADS to simulate Noise Figure using a large-signal transistor ...
Steve Long
COMS集成锁相环电路设计 张刚
A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled ...
Wenbin Huang & Lianxi Liu & Xufeng Liao & Chengzhi Xu & Yonyuan Li
Enhanced phase noise modeling of fractional-N frequency synthesizers
H. Arora;N. Klemmer;J.C. Morizio;P.D. Wolf
ISSCC2021-T2-Fund[..] of Memory Subsystem Design for HPC and ...
A 1.5-V, 1.5-GHz CMOS Low Noise Amplifier - Solid-State Circuits, ...
IEEE
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
Session 5
python 数值分析
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IP3 and Intermodulation Guide | Maxim Integrated
Session 8
数字信号处理的FPGA实现(第3版[..]
信号与系统 MATLAB综合实验
Accurate and Rapid Measurement of IP2 and IP3
Ken Kundert