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12位50Msps流水线A D转换器的研究与设计

12位50Msps流水线A D转换器的研究与设计

A low-power small-area /spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...

Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang

Sahrling M. Analog Circuit Simulators for Integrated Circuit Designers 2021

Sahrling M. Analog Circuit Simulators for Integrated Circuit ...

$Wideband RF PLL fractional/integer frequency synthesizer with integrated VCOs and LDOs$

Wideband RF PLL fractional/integer frequency synthesizer with ...

STMICROELECTRONICS

Power Management Techniques for Integrated Circuit Design

Power Management Techniques for Integrated Circuit Design

Signal and Power Integrity - Simplified, Third edition

Signal and Power Integrity - Simplified, Third edition

集成电路版图设计 [陆学斌主编] 2012年版

集成电路版图设计 [陆学斌主编] 2012年版

Cadence高速电路板设计与仿真信号与电源完整性分析第5版

Cadence高速电路板设计与仿真信号与电源完整性分析第5版

ISSCC2021-T4-Measuring and Evaluating the Security Level of Circuits

ISSCC2021-T4-Meas[..] and Evaluating the Security Level of ...

模拟集成电路与系统 Analog Integrated Circuits and Systems

模拟集成电路与系统 Analog Integrated Circuits and Systems

池保勇编著

Middlebrook Part 1

Middlebrook Part 1

数字信号处理时域离散随机信号处理

数字信号处理时域离散随机信号处理

PLL Perfomance, Simulation, and Design

PLL Perfomance, Simulation, and Design

Constraining Designs for Synthesis and Timing Analysis A Practical Guide to Synopsys Design Constraints (SDC) (Sridhar Gangadharan, Sanjay Churiwala (auth.)) (z-lib.org)

Constraining Designs for Synthesis and Timing Analysis A Practical ...

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

A fast-settling CMOS op amp for SC circuits with 90-dB DC gain

K. Bult;G.J.G.M. Geelen

离散时间控制系统（第二版） Katsuhiko ； Ogata (z-lib.org)

离散时间控制系统（第二版） Katsuhiko ； Ogata (z-lib.org)

A gm/ID Based Methodology for the Design of CMOS Analog Circuits andd Its Application to the S - Solid-State Circuits, IEEE Journal of

A gm/ID Based Methodology for the Design of CMOS Analog Circuits ...

高性能流水线模数转换器及其数字校准技术研究贾华宇

高性能流水线模数转换器及其数字校准[..] 贾华宇

Category: reconciliation sublayer

IEEE Standard for Ethernet

IEEE Standard for Ethernet