ISSCC2021-SC1-Int[..] to PLLs Phase Noise, Modeling, and Key ...
未知
2.7Gbps收发器中LVDS驱动[..]
Session 16: Computation in Memory
CMOS Circuit Design, Layout, and Simulation, 3rd Edition (IEEE ...
R. Jacob Baker
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(英)DouglasSelf著
Enhanced phase noise modeling of fractional-N frequency synthesizers
H. Arora;N. Klemmer;J.C. Morizio;P.D. Wolf
RFIC2 Razavi Solution
AN 812: Platform Designer System Design Tutorial
Intel Corporation
maloberti data converters
Digital integrated circuit design using verilog and systemverilog ...
Advanced Computational Electromagnetic Methods and Applications
Yu, Li, Elsherbeni, Rahmat-Samii, Editors
SCHMITT TRIGGER CIRCUIT USING MOS TRANSISTORS AND HAVING CONSTANT ...
Algorithms for VLSI Physical Design Automation, 3E
Naveed Sherwani
Microsoft Word - translator_prefac[..]
Zhiping Yu
集成电路设计中的电源管理技术
Founder Electronics Ltd
CMOS-Voltage-Refe[..]
4<8=8AB@0B>@
锁相环(PLL)电路设计与应用
(日)远坂俊昭 著 何希才译
ISSCC2021-T11-Ult[..] Power Wireless Receiver Design
A simple three-terminal IC bandgap reference
A.P. Brokaw