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DIFFERENTIAL EQUATIONS WITH APPLICATIONS AND HISTORICAL NOTES

DIFFERENTIAL EQUATIONS WITH APPLICATIONS AND HISTORICAL NOTES

George F. Simmons

Scaling <formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...

Shih-An Yu & Peter R. Kinget

finite elemennt anlysis in ansys

finite elemennt anlysis in ansys

Parallel Sparse Direct Solver for Integrated Circuit Simulation by Xiaoming Chen, Yu Wang, Huazhong Yang (z-lib.org)

Parallel Sparse Direct Solver for Integrated Circuit Simulation ...

Computing ACPR from 1Tone HB ADS 2011

Computing ACPR from 1Tone HB ADS 2011

模拟电子技术基础第5版

模拟电子技术基础第5版

清华大学电子学教研组编；童诗白，华成英原主编；华成英，[..]

Pieter Harpe, Andrea Baschirotto, Kofi A. A. Makinwa eds. High-Performance AD and

Pieter Harpe, Andrea Baschirotto, Kofi A. A. Makinwa eds. High-Performance ...

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Stephen Brown & Zvonko Vranesic

CH01

CH01

一种应用于LDO的CMOS误差放大器设计

一种应用于LDO的CMOS误差放大器设计

SAR A／D转换器中电容失配问题的分析

SAR A／D转换器中电容失配问题的分析

FinFET Devices for VLSI Circuits and Systems

FinFET Devices for VLSI Circuits and Systems

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques [Paper] - Solid-State Circuits, IEEE Journal of

Low-Jitter Process-Independent DLL and PLL Based on Self-Biased ...

Design of Bandgap Reference and Current Reference Generator with Low Supply Voltage

Design of Bandgap Reference and Current Reference Generator ...

Continuous-Time Delta-Sigma Modulators for High-Speed AD Conversion Theory, Practice and Fundamental Performance Limits by James A. Cherry, W. Martin Snelgrove (auth.) (z-lib.org)

Continuous-Time Delta-Sigma Modulators for High-Speed AD Conversion ...

Microsoft Word - Telescopic.doc

Microsoft Word - Telescopic.doc

Analog Behavioral Modeling with the Verilog-A Language

Analog Behavioral Modeling with the Verilog-A Language

ISSCC2017-24 Visuals(2)

ISSCC2017-24 Visuals(2)

Category: phase-locked loop (PLL)

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...

Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi