VLSI Physical Design: From Graph Partitioning to Timing Closure
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Digital Design Netlisting and Simulation SKILL Refer ence
Inc. Cadence Design Sys tems
Session 10
未知
恒流LDO型自光LED驱动芯片的设计研究
NoiseDesign.dvi
Wiener-Khinchin theorem
PCI Express PHY v1.0 LogiCORE IP Product Guide
Xilinx, Inc.
低功耗逐次逼近寄存器模数转换器综述 丁召明 (1)
CNKI
Microsoft Word - translator_prefac[..]
Zhiping Yu
全差分运算放大器设计-tangzh[..]
chwtang
逐达逼近型模数转换器的低功耗与高速[..]
华侨大学模拟IC实验8 无缓冲两级运放设计
USER
High-Frequency Integrated Circuits
Voinigescu, Sorin
用于低相位噪声LC VCO的低噪声可调LDO的设计
CMOS模拟IP线性集成电路 (1)
Session 19
A 1 GHz CMOS RF Front-End IC for a Direct-Conversion Wireless ...
IEEE
CN104391533A-High[..] (power supply rejection ratio) LDO (low ...
IEEE Std 802.11g-2003 [Amendment to IEEE Std 802.11, 1999 Edition ...
LAN/MAN Standards Committee of the IEEE Computer Society