综合与Design Compiler
阳晔
Session 20
未知
Practical RF Circuit Design for Modern Wireless Systems_ Passive ...
Name
射频集成电路
John
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
基准电压源和线性稳压器的设计-ta[..]
lmliu
温度补偿的30nA CMOS电流源及在LDO中的应用
计算电磁学 by 王秉中,邵维 (z-lib.org)
CNKI
模拟集成电路分析与设计 洪志良
纳米级CMOS逐次逼近A D转换器设计研究与实现
通信标准对数据转换器的要求V1.0
ISSCC2021-SC3-Clo[..] Clock Distribution, and Clock Management ...
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
Fast analytical techniques for electrical and electronic circuits
Vatche Vorperian
MT-001: Taking the Mystery out of the Infamous Formula,'SNR ...
Walt Kester
Session 36: Hardware Security
verilog HDL那些事
akuei2
Design Optimization of Power and Area of Two-Stage CMOS Operational ...
Telugu Maddileti;Govindarajulu Salendra;Chandra Mohan Reddy ...
Embedded Design Handbook
Intel Corporation