Session 31: Analog Techniques
未知
untitled
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai
模拟集成电路分析与设计 洪志良
Session 8
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx, Inc.
Numerical Analysis (Richard L. Burden, J. Douglas Faires etc.) ...
eetop.cn TN07CLDR001 1 3
数字通信同步技术的MATLAB与F[..] Altera Verilog版 [杜勇 编著] 2015年版
High Performance SAR-based ADC Design in Deep Sub-micron CMOS
lei sun
EE145C UCSB RFCMOS Communication Circuits and Systems g
Computational electromagnetism variational formulations, complementarity, ...
高性能音频Delta-Sigma数[..]
基于零极点追踪的高稳定性片内LDO[..]
抗浪涌静电器件防护机理与片上集成实验研究
Legend User
Generate ESD Source in ADS
TU,NASH (K-Taiwan,ex1)
Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-MM Interface ...
Intel Corporation
基于全反馈的高稳定性LDO线性稳压器
Questa Verification IP Data Book
Mentor Graphics Corporation