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COMS集成锁相环电路设计张刚

COMS集成锁相环电路设计张刚

Distributed MOS varactor biasing for VCO gain equalization in 0.13 /spl mu/m CMOS technology

Distributed MOS varactor biasing for VCO gain equalization in ...

J. Mira & T. Divel & S. Ramet & J.-B. Begueret & Y. Deval

模拟IC设计

模拟IC设计

Preparation of Papers in Two-Column Format for the Proceedings of the 2004 Sarnoff Symposium

Preparation of Papers in Two-Column Format for the Proceedings ...

Numerical Methods in Engineering with Python (2005)

Numerical Methods in Engineering with Python (2005)

低压、低功耗、高精度的逐次逼近型

低压、低功耗、高精度的逐次逼近型

TMTT 202212

TMTT 202212

数值分析（第5版）习题解答 (李庆扬) (z-lib.org)

数值分析（第5版）习题解答 (李庆扬) (z-lib.org)

Calibre® Interactive (Classic GUI) User's Manual

Calibre® Interactive (Classic GUI) User's Manual

Siemens Industry Software

Chap1_20160228_4.dvi

Chap1_20160228_4.dvi

DIT-FFT至简设计实现法

DIT-FFT至简设计实现法

Precise delay generation using coupled oscillators

Precise delay generation using coupled oscillators

J.G. Maneatis & M.A. Horowitz

Session 17: DC-DC Converters

Session 17: DC-DC Converters

一种超低静态功耗LDO的设计

一种超低静态功耗LDO的设计

Synthesis and Optimization of Digital Circuits (Giovanni De Micheli) (z-lib.org)

Synthesis and Optimization of Digital Circuits (Giovanni De ...

EESM692

EESM692

Prof. Alex Leung

CN104601160B-灿芯半导体2017-带ESD的高速输出级

CN104601160B-灿芯半导[..]

PoleZero.dvi

PoleZero.dvi

Category: This core implements a JESD204B interface supporting a line rate of up to 12.5 Gb/s on 1- 12 lanes using GTX or GTH transceivers in Zynq-7000 AP SoC devices

JESD204 v7.2 LogiCORE IP Product Guide (PG066)

JESD204 v7.2 LogiCORE IP Product Guide (PG066)