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Verilog数字系统设计教程

Verilog数字系统设计教程

集成稳压电路系统鲁棒性与快速响应研究

集成稳压电路系统鲁棒性与快速响应研究

Distributed MOS varactor biasing for VCO gain equalization in 0.13 /spl mu/m CMOS technology

Distributed MOS varactor biasing for VCO gain equalization in ...

J. Mira & T. Divel & S. Ramet & J.-B. Begueret & Y. Deval

3P-EBK: CALCULUS EARLY TRANSCENDENTALS

3P-EBK: CALCULUS EARLY TRANSCENDENTALS

Signal and Power Integrity - Simplified, Third edition

Signal and Power Integrity - Simplified, Third edition

离散数学及其应用

离散数学及其应用

基于运算放大器和模拟集成电路的电路设计(第3版)——Design with Operational Amplifiers and Analog Integrated Circuits

基于运算放大器和模拟集成电路的电路[..] with Operational Amplifiers and Analog ...

Sergio Franco 著

7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)

7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)

Book.DVI

Book.DVI

Analysis and Design of Monolithic, High PSR, Linear Regulators for SoC Applications

Analysis and Design of Monolithic, High PSR, Linear Regulators ...

Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet

Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet

共源共栅实验五

共源共栅实验五

华侨大学模拟IC实验8 无缓冲两级运放设计

华侨大学模拟IC实验8 无缓冲两级运放设计

Design of Bandgap Reference and Current Reference Generator with Low Supply Voltage

Design of Bandgap Reference and Current Reference Generator ...

A0130105

A0130105

e采样与adc

e采样与adc

高精度sigma-delta ADC设计研究与实现

高精度sigma-delta ADC设计研究与实现

LDO设计-tangzhangwen

LDO设计-tangzhangwen

Category: This core connects one or more AXI memory-mapped master devices to one or more memory-mapped slave devices.

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)

AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)