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Discover (Random Books)

ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application Considerations

ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application ...

未知

Session 6: High-Performance Receivers and Transmitters for Sub-6GHz Radios

Session 6: High-Performance Receivers and Transmitters for Sub-6GHz ...

未知

Spectre Circuit Simulator Reference

Spectre Circuit Simulator Reference

Inc. Cadence Design Sys tems

锁相环(PLL)电路设计与应用

锁相环(PLL)电路设计与应用

(日)远坂俊昭 著 何希才译

NoiseDesign.dvi

NoiseDesign.dvi

未知

半导体物理与器件 (第三版)

半导体物理与器件 (第三版)

(美)尼曼著 赵毅强 姚素英 解晓东等译

Virtuoso Parameterized Cell Reference

Virtuoso Parameterized Cell Reference

Inc. Cadence Design Sys tems

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP Product Guide (PG055)

AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...

Xilinx, Inc.

Book.DVI

Book.DVI

未知

光通信集成电路设计第2版中文——拉扎维

光通信集成电路设计第2版中文——拉扎维

未知

IEEE Standard for Information Technology—Telecommunications and information exchange between systems—LANs and MANs—Specific requirements—Part 11: WLAN MAC and PHY Specifications—Amendment 5: Enhancements for Higher Throughput

IEEE Standard for Information Technology—Teleco[..] and information ...

LAN/MAN Standards Committee of the IEEE Computer Society

NumericalOptimization

NumericalOptimiza[..]

未知

微波射频电路设计与仿真100例

微波射频电路设计与仿真100例

Administrator

verilog HDL那些事

verilog HDL那些事

akuei2

LDO LINEAR REGULATOR WITH  IMPROVED TRANSIENT RESPONSE

LDO LINEAR REGULATOR WITH IMPROVED TRANSIENT RESPONSE

未知

Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: Autozeroing, Correlated Double - Proceedings of the IEEE

Circuit Techniques for Reducing the Effects of Op-Amp Imperfections: ...

IEEE

Digital Control

Digital Control

未知

高速数字电路设计中信号完整性分析与研究

高速数字电路设计中信号完整性分析与研究

未知

Category: physical coding sublayer

IEEE Standard for Ethernet

IEEE Standard for Ethernet

未知

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