一种无片外电容LDO的瞬态增强电路设计
未知
Next-Generation ADCs, High-Performance Power Management, and ...
A low-power small-area /spl plusmn/7.28-ps-ji[..] 1-GHz DLL-based ...
Chulwoo Kim & In-Chul Hwang & Sung-Mo Kang
锁相环(PLL)电路设计与应用
(日)远坂俊昭 著 何希才译
CMOS模拟集成电路
王永生
摘要
xbma
Session 6
0132642786.pdf
Neil H. E. Weste
学校代码: 10246
tcheng
CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...
D.J. Foley;M.P. Flynn
Digital integrated circuit design using verilog and systemverilog ...
ISSCC2020-01 Visuals
Steve Bonney
a-new-semiconduct[..]
The Design of Low-Noise Bandgap References - Circuits and Systems ...
IEEE
自适应滤波器原理
(美)赫金 & 郑宝玉等译
Computing the continuous discretely. Integer-point enumeration ...
自动控制原理(胡寿松)
微软用户
无线通信中的射频收发系统设计(英文版)
IEEE Standard for Ethernet