基于CMOS工艺的全芯片ESD保护[..]
未知
Accurate and Rapid Measurement of IP2 and IP3
Ken Kundert
Triple-Speed Ethernet Intel® FPGA IP User Guide
Intel Corporation
Session 22: Terahertz for Communication and Sensing
锁相环(PLL)电路设计与应用
(日)远坂俊昭 著 何希才译
线性代数教材(同济五版+学习辅导与[..]
Acampo GmbH
PCI Express Base r3.0
一种基于内部迟滞比较器的新型RC振荡器
Operational Transconductance Amplifiers “OTAs”
Bernhard Boser
HFIC chapter 7 low-noise amplifier design
带温度补偿的扩频振荡器研究与设计
Using ADS to simulate Noise Figure using a large-signal transistor ...
Steve Long
Digital Control
Digital Design Netlisting and Simulation SKILL Refer ence
Inc. Cadence Design Sys tems
ISM-PLL
Session 30: Non-Volatile Memories
A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai
集成电路静态时序分析与建模
刘峰编著
Enhanced phase noise modeling of fractional-N frequency synthesizers
H. Arora;N. Klemmer;J.C. Morizio;P.D. Wolf