理工书库 lilin | Category: IEEE Journal of Solid-State Circuits;2001;36;3;10.1109/4.910480

Discover (Random Books)

Design of class AB output stages using the structural methodology

Design of class AB output stages using the structural methodology

V. Ivanov & I. Filanovsky

概率论与数理统计 (同济大学数学系) (Z-Library)

概率论与数理统计 (同济大学数学系) (Z-Library)

模拟集成电路分析与设计洪志良

模拟集成电路分析与设计洪志良

Harmonic Balance for Nonlinear Vibration Problems

Harmonic Balance for Nonlinear Vibration Problems

PrimeSim� CCK Reference Manual

PrimeSim� CCK Reference Manual

Session 17: DC-DC Converters

Session 17: DC-DC Converters

Method of Moments for 2D Scattering Problems

Method of Moments for 2D Scattering Problems

Christophe Bourlier

基于XILINX FPGA的OFDM通信系统基带设计

基于XILINX FPGA的OFDM通信系统基带设计

半导体工艺和器件仿真工具Silvaco TCAD

半导体工艺和器件仿真工具Silvaco TCAD

Session 35

Session 35

Design of Analog CMOS Integrated Circuits

Design of Analog CMOS Integrated Circuits

Adaptive Filter Theory 5/E

Adaptive Filter Theory 5/E

AM-PM distorion

AM-PM distorion

简并点优化的高性能带隙基准电路应建华

简并点优化的高性能带隙基准电路应建华

基于FPGA的嵌入式图像处理系统设计原魁[译]

基于FPGA的嵌入式图像处理系统设计原魁[译]

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled Buck Converter With A<sup>2</sup>-Comparator and Sleep-Time Detector for IoT Application

A 240-nA Quiescent Current, 95.8% Efficiency AOT-Controlled ...

Wenbin Huang & Lianxi Liu & Xufeng Liao & Chengzhi Xu & Yonyuan Li

Intel® Quartus® Prime Standard Edition User Guide Platform Designer

Intel® Quartus® Prime Standard Edition User Guide Platform Designer

Intel Corporation

ISSCC2021-SC3-Clocking, Clock Distribution, and Clock Management in WirelineWireless Subsystems

ISSCC2021-SC3-Clo[..] Clock Distribution, and Clock Management ...

Category: IEEE Journal of Solid-State Circuits;2001;36;3;10.1109/4.910480

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and temperature-compensated tunable oscillator

CMOS DLL-based 2-V 3.2-ps jitter 1-GHz clock synthesizer and ...

D.J. Foley;M.P. Flynn