Verilog HDL Design Examples
Joseph Cavanagh
DesignWare Synthesizable Components for AMBA 3 AXI, and AMBA ...
Synopsys, Inc.
SystemVerilog 验证方法学 - Verification Methodology Manual for SystemVerilog
Janick Bergeron & Eduard Cemy & Alan Hunter & Andrew Nightingale 著 & 夏宇闻 译
基于延迟锁相环的时钟发生器设计
未知
Low-noise monolithic amplifier design: Bipolar versus CMOS
低压低功耗CMOS带隙电压基准及启[..] 许长喜
EE214B Advanced Analog Integrated Circuit Design
man_mentor_vip_ax[..]
merickso
计算电磁学要论 by 盛新庆 (z-lib.org)
CNKI
Session 20: High-Performance VCOs
模拟集成电路设计
数字电子技术基础
阎石主编
ZigBee低中频接收机中复数滤波[..]
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
一种低压CMOSLDO稳压电源电路
Session 30
A bandgap reference using chopping for reduction of
Operational Transconductance Amplifiers “OTAs”
Bernhard Boser
Analysis and Design of ESD Protection for Robust Low-Power Pierce ...
Kim B. Ostman & Erlend Strandvik & Phil Corbishley & Tor Oyvind Vedal & Mika Salmi