Embedded Mixed-Signal IP Development Methodology in 90nm CMOS ...
Rakesh H. Patel & William Bereza
2019 Book Digital Subsampling Phase Lock Techniques for Frequency ...
未知
Using ADS to simulate Noise Figure using a large-signal transistor ...
Steve Long
Design Procedures for Three-Stage CMOS OTAs With Nested-Miller ...
Session 15
Session 36: Hardware Security
Universal Serial Bus 3.0 Specification
Avalon Verification IP Suite User Guide
Altera Corporation
Session 18: Biomedical Devices, Circuits, and Systems
Digital Design Netlisting and Simulation SKILL Refer ence
Inc. Cadence Design Sys tems
深入理解LINUX网络技术内幕
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin
Design of Analog CMOS Integrated Circuits
Razavi
2-Stage OTA Design
一种高精度的CMOS带隙基准电压源
2017 Book OperationalAmplif[..]
射频微电子学 (Behzad Razavi) (Z-Library)
一种快速瞬态响应的无片外电容LDO[..]
7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
Xilinx, Inc.