AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)
Xilinx, Inc.
2-Stage OTA Design
未知
ISSCC2021-SC3-Clo[..] Clock Distribution, and Clock Management ...
Design Procedure for Two-Stage CMOS Transconductance Operational ...
ISSCC2021-SC2-PLL Architectures, Tradeoffs, and Key Application ...
Verification of SD/MMC Controller IP Using UVM
High Efficiency RF and Microwave Solid State Power Amplifiers
Paolo Colantonio, Franco Giannini & Ernesto Limiti
SAR A／D转换器中电容失配问题的分析
IEEE Std 802.11b-1999
PHASE-INTERPOLATOR BASED PLL FREQUENCY SYNTHESIZER
High-Speed Architecture for a Programmable Frequency Divider ...
IEEE
electronic devices
Thomas L. Floyd
高效率 PWM 控制电流型 DC-DC
Lenovo User
A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS process
Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Yin-Zu Lin
Designing Audio Power Amplifiers (Bob Cordell) (Z-Library)
两种新型CMOS带隙基准电路 程军
CNKI
ANALOG CMOS IC DESIGN 模拟CMOS集成电路设计
魏廷存 & 陈莹梅 & 胡正飞
Optimum Feedback Amplifier Design For Control Systems
Timothy E. Biesecker
IEEE Standard for Information Technology—Teleco[..] and information ...
LAN/MAN Standards Committee of the IEEE Computer Society