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一种新型CMOS误差放大电路的设计 来新泉
锁相环(PLL)电路设计与应用
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Constraining Designs for Synthesis and Timing Analysis A Practical ...
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共源共栅实验五
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Session 25
Avalon Tri-state Conduit Components User Guide
Altera Corporation
A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process
Wenzha Yang & Yi Zhang & Enwen Dai & ZhiLin Feng & Wei Li
模拟集成电路设计精粹英文版
Session 18: Biomedical Devices, Circuits, and Systems
Advanced data converters G Manganaro
IEEE Standard for Ethernet