理工书库 lilin | Category: 【页数】 319

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Systematic Design of Analog CMOS Circuits

Systematic Design of Analog CMOS Circuits

Microsoft PowerPoint - PLL_UT_tutorial_AdrianMaxim_final.ppt

Microsoft PowerPoint - PLL_UT_tutorial_A[..]

ISSCC2021-T4-Measuring and Evaluating the Security Level of Circuits

ISSCC2021-T4-Meas[..] and Evaluating the Security Level of ...

Quantus Extraction Users Manual

Quantus Extraction Users Manual

CMOS 集成电路设计手册第3版·模拟电路篇=CMOS CIRCUIT DESIGN LAYOUT AND SIMULATION 3RD EDITION

CMOS 集成电路设计手册第3版·模拟电路篇=CMOS CIRCUIT DESIGN LAYOUT AND SIMULATION ...

线性代数教材(同济五版+学习辅导与习题全解)

线性代数教材(同济五版+学习辅导与[..]

ISSCC2021-SC1-Introduction to PLLs Phase Noise, Modeling, and Key Wireless Design Considerations

ISSCC2021-SC1-Int[..] to PLLs Phase Noise, Modeling, and Key ...

一种用于LDO的低功耗带隙基准电压源

一种用于LDO的低功耗带隙基准电压源

$Enhanced phase noise modeling of fractional-N frequency synthesizers$

Enhanced phase noise modeling of fractional-N frequency synthesizers

H. Arora;N. Klemmer;J.C. Morizio;P.D. Wolf

《ModelSim电子系统分析及仿真》

《ModelSim电子系统分析及仿真》

一种具有温度补偿高电源抑制比的带隙基准源何捷 (1)

一种具有温度补偿高电源抑制比的带隙基准源何捷 (1)

Session 35

Session 35

PLL WITH LOW SPURS

PLL WITH LOW SPURS

哈尔滨工业大学硕士毕业论文模板

哈尔滨工业大学硕士毕业论文模板

一款超低噪声快速启动的CMOS带隙基准电路设计刘鸿雁

一款超低噪声快速启动的CMOS带隙[..] 刘鸿雁

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop Filter PLL Using a Fast Phase-Error Correction Technique

A Low-Jitter and Low-Reference-Spur Ring-VCO-Based Switched-Loop ...

Yongsun Lee & Taeho Seong & Seyeon Yoo & Jaehyouk Choi

一种具有温度补偿高电源抑制比的带隙基准源何捷

一种具有温度补偿高电源抑制比的带隙基准源何捷

Scaling <formula formulatype="inline"><tex Notation="TeX">$LC$</tex></formula> Oscillators in Nanometer CMOS Technologies to a Smaller Area But With Constant Performance

Scaling <formula formulatype="inli[..] Notation="TeX">$L[..] ...

Shih-An Yu & Peter R. Kinget

Category: 【页数】 319

Verilog数字VLSI设计教程

Verilog数字VLSI设计教程

【作者】李林编著