A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
运放仿真方法整理
USER
Session 22: Terahertz for Communication and Sensing
未知
StarRC User Guide and Command Reference
Synopsys, Inc.
Avalon Verification IP Suite User Guide
Altera Corporation
Session 25: DRAM
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
Xilinx, Inc.
TI-CICC2006-A Sub-i V Low-Noise Bandgap Voltage Reference
工程电路分析
LDO设计小结一
zeng zhen
FinFET Modeling for IC Simulation and Design
4<8=8AB@0B>@
Artificial Intelligence A Modern Approach (4th Edition)
Session 9
RISC-V手册
Da
计算PSRR的新方法
雨林木风
Constraining Designs for Synthesis and Timing Analysis A Practical ...
Next-Generation ADCs, High-Performance Power Management, and ...
CN102393785B-砂力杰-[..]
AXI Interconnect v2.1 LogiCORE IP Product Guide (PG059)
JESD204 v7.2 LogiCORE IP Product Guide (PG066)
Xilinx PG153 LogiCORE IP AXI Quad Serial Peripheral Interface ...
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx DS534, FIR Compiler v5.0, Data Sheet