ESD in Silicon Integrated Circuits
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tcsii.2005.A new modeling and optimization of gain-boosted cascode ...
Session 11: Advanced Wireline Links and Techniques
ISSCC2021-SC1-Int[..] to PLLs Phase Noise, Modeling, and Key ...
A 2.488–11.2 Gb/s multi-protocol SerDes in 40nm low-leakage ...
Socrates D. Vamvakos & Claude R. Gauthier & Chethan Rao & Karthisha Ramoshan Canagasaby & Prashant Choudhary & Sanjay Dabral & Shaishav Desai & Mahmudul Hassan & K.C. Hsieh & Bendik Kleveland & Gurupada Mandal & Richard Rouse & Ritesh Saraf & Alvin Wang & Jason Yeung & Khaldoon Abugharbieh & Ying Cao
A 2-dB noise figure 900-MHz differential CMOS LNA - Solid-State ...
Perl语言入门 第六版
基于XILINX FPGA的OFDM通信系统基带设计
Session 15
Design of Chopper-Stabilized Amplifiers With Reduced Offset ...
一种自参考结构的高速高精度片上时钟[..]
PLL 设计仿真及应用
Roland E. Best
Session 32: Frequency Synthesizers
一种快速瞬态响应LDO的设计与实现
TOM
VLSI Physical Design: From Graph Partitioning to Timing Closure
Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu
Operational Amplifiers Theory and Design (Johan Huijsing (auth.)) ...
CMOS射频集成电路分析与设计 清华池保勇
lnaDesign2
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx, Inc.
Xilinx DS249 LogiCORE IP CORDIC v4.0, Data Sheet,
Xilinx DS534, FIR Compiler v5.0, Data Sheet