ISSCC2021-SC1
未知
Vivado Design Suite User Guide: Logic Simulation (UG900)
Xilinx, Inc.
A 0.775mW 10-bit 40-MS/s SAR ADC in 0.18μm CMOS process
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BesserWM35.vp:Cor[..] 7.0
jpaiva
全数字锁相环建模及分析代码-2014
半导体工艺和器件仿真工具Silvaco TCAD
唐龙谷
Universal Serial Bus 3.0 Specification
CN103036558B-SMIC[..]
CMOS射频集成电路分析与设计 清华池保勇
哈尔滨工业大学硕士毕业论文模板
yinhf
electronic devices
Thomas L. Floyd
COMS集成锁相环电路设计 张刚
PrimeSim� EMIR Reference Manual
Inc. Synopsys
Harmonic balance finite element method applications in nonlinear ...
CMOS带隙基准源研究现状 幸新鹏
Operational Amplifiers Theory and Design (Johan Huijsing (auth.)) ...
A Low Power Two Stages CMOS OpAmp
Understanding Jitter and Phase Noise : A Circuits and Systems ...
Nicola Da Dalt; Ali Sheikholeslami & Ali Sheikholeslami
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx DS534, FIR Compiler v5.0, Data Sheet