Session 29V
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Elementary Differential Equations and Boundary Value Problems
William E. Boyce & Richard C. Diprima & Douglas B. Meade
7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge ...
Xilinx, Inc.
Verification of SD/MMC Controller IP Using UVM
Session 35: Adaptive Digital Techniques for Variation Tolerant ...
Cadence SKILL Lan guage Reference
Inc. Cadence Design Sys tems
Analog-to-Digital Conversion 3rd
计算电磁学 by 王秉中,邵维 (z-lib.org)
CNKI
CN101140511B-硅谷数模[..] carry binary adder
eetop.cn TN07CLDR001 1 3
高速信令-抖动建模-分析预算
Python API Reference Manual
Inc. Synopsys
CMOS Mixed-Signal Circuit Design, 2nd Ed
Distributed MOS varactor biasing for VCO gain equalization in ...
J. Mira & T. Divel & S. Ramet & J.-B. Begueret & Y. Deval
ADI 技术指南合集
High-Speed Architecture for a Programmable Frequency Divider ...
IEEE
2014 PhD-Thesis BAG A Designer-Oriented Framework for the Development ...
Numerical Analysis
Richard L. Burden
Xilinx DS558, LogiCORE IP DDS Compiler v4.0, Data Sheet
Xilinx DS534, FIR Compiler v5.0, Data Sheet