理工书库 lilin | Category: Avalon Memory-Mapped

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Session 8: Ultra-High-Speed Wireline

Session 8: Ultra-High-Speed Wireline

简并点优化的高性能带隙基准电路应建华

简并点优化的高性能带隙基准电路应建华

Session 6

Session 6

Gray Hurst Analysis and Design of Analog Integra

Gray Hurst Analysis and Design of Analog Integra

untitled

untitled

Jespers-The gm ID Methodology, a sizing tool

Jespers-The gm ID Methodology, a sizing tool

Algorithms for VLSI Physical Design Automation, 3E

Algorithms for VLSI Physical Design Automation, 3E

Naveed Sherwani

信号与系统（奥本海姆）

信号与系统（奥本海姆）

Numerical Methods in Engineering with Python (2005)

Numerical Methods in Engineering with Python (2005)

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Stephen Brown & Zvonko Vranesic

深入Linux内核架构

深入Linux内核架构

带ESD保护结构的IO单元库的设计

带ESD保护结构的IO单元库的设计

Numerical Methods for Engineering: An introduction using MATLAB® and computational electromagnetics examples 2nd Edition

Numerical Methods for Engineering: An introduction using MATLAB® ...

Karl F. Warnick

适宜于系统集成的高速高精度模数转换电路设计技术研究-李福乐

适宜于系统集成的高速高精度模数转换[..]

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Fundamentals of Digital Logic with Verilog Design, THIRD EDITION

Stephen Brown & Zvonko Vranesic

ESD Design and Synthesis

ESD Design and Synthesis

高速串行接口时钟数据恢复电路设计研究

高速串行接口时钟数据恢复电路设计研究

DCDC变换器工作原理及设计

DCDC变换器工作原理及设计

Category: Avalon Memory-Mapped

Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-MM Interface for PCI Express* User Guide

Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-MM Interface ...

Intel Corporation

Avalon® Interface Specifications

Avalon® Interface Specifications

Intel Corporation

Avalon Verification IP Suite User Guide

Avalon Verification IP Suite User Guide

Altera Corporation