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LDO的三种频率补偿方案实现

LDO的三种频率补偿方案实现

EDA与IC设计 CMOS集成电路后端设计与实战

EDA与IC设计 CMOS集成电路后端设计与实战

电路原理（第7版）

电路原理（第7版）

信号与系统 2nd 西蒙赫金

信号与系统 2nd 西蒙赫金

Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-MM Interface for PCI Express* User Guide

Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-MM Interface ...

Intel Corporation

学校代码 10530 学号 201110061316

学校代码 10530 学号 201110061316

高速数字电路设计中信号完整性分析与研究

高速数字电路设计中信号完整性分析与研究

Chopper Stabilized Amplifiers

Chopper Stabilized Amplifiers

7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge (XAPP1286)

7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge ...

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

参考书芯片接口库IO LIBRARY和ESD电路的研发设计应用 (OCR) 王国立

PrimeSim� EMIR Reference Manual

PrimeSim� EMIR Reference Manual

Harmonic Balance for Nonlinear Vibration Problems

Harmonic Balance for Nonlinear Vibration Problems

Session 18

Session 18

高等数学第7版上

高等数学第7版上

同济大学数学系编

Computational Intelligence in Analog and Mixed-Signal (AMS) and Radio-Frequency (RF) Circuit Design by Mourad Fakhfakh, Esteban Tlelo-Cuautle, Patrick Siarry (eds.) (z-lib.org)

Computational Intelligence in Analog and Mixed-Signal (AMS) ...

VLSI Physical Design: From Graph Partitioning to Timing Closure

VLSI Physical Design: From Graph Partitioning to Timing Closure

Andrew B. Kahng, Jens Lienig, Igor L. Markov, Jin Hu

一种用于低功耗LDO的CMOS电压基准设计

一种用于低功耗LDO的CMOS电压[..]

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

A 10b 100MS/s 1.13mW SAR ADC with binary-scaled error compensation

Chun-Cheng Liu & Soon-Jyh Chang & Guan-Ying Huang & Ying-Zu Lin & Chung-Ming Huang & Chih-Hao Huang & Linkai Bu & Chih-Chung Tsai

Category: media independent interface

IEEE Standard for Ethernet

IEEE Standard for Ethernet