eetop.cn Matching
未知
高性能低压差线性稳压器研究与设计
Abraham uta GPIO ESD
Administrator
CN104391533A-High[..] (power supply rejection ratio) LDO (low ...
0132642786.pdf
Neil H. E. Weste
LDO LINEAR REGULATOR WITH IMPROVED TRANSIENT RESPONSE
eetop.cn 高增益恒跨导低失调轨至轨运算放大器的设计 彭新朝
CNKI
Session 13
数值分析（第5版）习题解答
高速低功耗逐次逼近型模数转换器的研[..]
模拟集成电路设计与仿真
何乐年
一种适用于高压电源管理的无输出电容[..]
一种新型CMOS误差放大电路的设计 来新泉
fluids-04-00159-v2
数值分析.Timothy Sauer.图灵中文扫描版
bingdian001.com
Cadence PVS Developers Guide
Inc. Cadence Design Sys tems
一种自参考结构的高速高精度片上时钟[..]
PCI Express PHY v1.0 LogiCORE IP Product Guide
Xilinx, Inc.
7 Series FPGAs Gen2 Integrated Block for PCIe to AXI4-Lite Bridge ...
AXI Memory Mapped to PCI Express (PCIe) Gen2 v2.8 LogiCORE IP ...
A Flexible, Low-Power Analog PLL for SoC and Processors in 14nm ...
Kuan-Yueh Shen & Syed Feruz Syed Farooq & Yongping Fan & Khoa Minh Nguyen & Qi Wang & Mark L. Neidengard & Nasser Kurd & Amr Elshazly
Intel® Arria® 10 and Intel® Cyclone® 10 GX Avalon®-MM Interface ...
Intel Corporation